zynq-rs/src/boot.rs

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use r0::zero_bss;
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use vcell::VolatileCell;
use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::cortex_a9::{asm, regs::*, cache, mmu};
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use crate::zynq::{slcr, mpcore};
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extern "C" {
static mut __bss_start: u32;
static mut __bss_end: u32;
static mut __stack_start: u32;
}
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/// `0` means: wait for initialization by core0
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static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
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#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn _boot_cores() -> ! {
const CORE_MASK: u32 = 0x3;
match MPIDR.read() & CORE_MASK {
0 => {
SP.write(&mut __stack_start as *mut _ as u32);
boot_core0();
}
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1 => {
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while CORE1_STACK.get() == 0 {
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asm::wfe();
}
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SP.write(CORE1_STACK.get());
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boot_core1();
}
_ => unreachable!(),
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}
}
#[naked]
#[inline(never)]
unsafe fn boot_core0() -> ! {
l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
mpcore.scu_invalidate.invalidate_all_cores();
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zero_bss(&mut __bss_start, &mut __bss_end);
let mmu_table = mmu::L1Table::get()
.setup_flat_layout();
mmu::with_mmu(mmu_table, || {
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mpcore.scu_control.start();
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ACTLR.enable_smp();
// TODO: Barriers reqd when core1 is not yet starting?
asm::dmb();
asm::dsb();
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crate::main();
panic!("return from main");
});
}
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#[naked]
#[inline(never)]
unsafe fn boot_core1() -> ! {
l1_cache_init();
let mpcore = mpcore::RegisterBlock::new();
mpcore.scu_invalidate.invalidate_core1();
let mmu_table = mmu::L1Table::get();
mmu::with_mmu(mmu_table, || {
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ACTLR.enable_smp();
// TODO: Barriers reqd when core1 is not yet starting?
asm::dmb();
asm::dsb();
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crate::main_core1();
panic!("return from main_core1");
});
}
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fn l1_cache_init() {
use crate::cortex_a9::cache::*;
// Invalidate TLBs
tlbiall();
// Invalidate I-Cache
iciallu();
// Invalidate Branch Predictor Array
bpiall();
// Invalidate D-Cache
//
// NOTE: It is both faster and correct to only invalidate instead
// of also flush the cache (as was done before with
// `dccisw()`) and it is correct to perform this operation
// for all of the L1 data cache rather than a (previously
// unspecified) combination of one cache set and one cache
// way.
dciall();
}
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pub struct Core1<S: AsMut<[u32]>> {
pub stack: S,
}
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impl<S: AsMut<[u32]>> Core1<S> {
pub fn stop(&self) {
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slcr::RegisterBlock::unlocked(|slcr| {
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
});
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}
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/// Reset and start core1
///
/// The stack must not be in OCM because core1 still has to
/// initialize its MMU before it can access DDR.
pub fn start(stack: S) -> Self {
let mut core = Core1 { stack };
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// reset and stop (safe to repeat)
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core.stop();
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let stack = core.stack.as_mut();
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let stack_start = &mut stack[stack.len() - 1];
unsafe {
CORE1_STACK.set(stack_start as *mut _ as u32);
}
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// Ensure stack pointer has been written to cache
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asm::dmb();
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// Flush cache-line
cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as u32);
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// wake up core1
slcr::RegisterBlock::unlocked(|slcr| {
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
});
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core
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}
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}