zynq-rs/libboard_zynq/src/lib.rs

#![no_std]

extern crate alloc;

/// Re-export so that dependents can always use the same version
pub use smoltcp;

pub mod slcr;
pub mod clocks;
pub mod uart;
pub mod devc;
pub mod stdio;
pub mod eth;
pub mod axi_hp;
pub mod axi_gp;
pub mod ddr;
pub mod mpcore;
pub mod flash;
pub mod time;
pub mod timer;
pub mod sdio;
pub mod logger;
pub mod ps7_init;

pub use libcortex_a9::pl310::L2Cache;

pub fn l2cache() -> L2Cache {
    const PL310_BASEADDR: usize = 0xF8F02000;
    L2Cache::new(PL310_BASEADDR)
}

pub fn setup_l2cache() {
    slcr::RegisterBlock::unlocked(|slcr| {
        assert_eq!(&slcr.unnamed1 as *const _ as u32, 0xF8000A1C);
        unsafe { slcr.unnamed1.write(0x020202); }
    });
    
    let mut l2 = l2cache();
    use log::info;
    info!("l2 aux={:08X}", l2.regs.aux_control.read());
    // TODO: set prefetch

    // Configure ZYNQ-specific latency
    l2.set_tag_ram_latencies(1, 1, 1);
    l2.set_data_ram_latencies(1, 2, 1);

    l2.disable_interrupts();
    l2.reset_interrupts();
    l2.invalidate_all();
    l2.enable();
}