zynq-rs/src/uart/regs.rs

106 lines
3.0 KiB
Rust
Raw Normal View History

2019-05-05 20:56:23 +08:00
use volatile_register::{RO, WO, RW};
2019-05-24 00:23:51 +08:00
use crate::{register, register_bit, register_bits, register_bits_typed, register_at, regs::*};
2019-05-07 05:56:53 +08:00
2019-05-24 00:23:51 +08:00
#[repr(u8)]
2019-05-21 07:30:54 +08:00
pub enum ChannelMode {
2019-05-22 07:42:24 +08:00
Normal = 0b00,
AutomaticEcho = 0b01,
LocalLoopback = 0b10,
2019-05-21 07:30:54 +08:00
RemoteLoopback = 0b11,
}
2019-05-24 00:23:51 +08:00
#[repr(u8)]
2019-05-21 08:53:59 +08:00
pub enum ParityMode {
EvenParity = 0b000,
OddParity = 0b001,
ForceTo0 = 0b010,
ForceTo1 = 0b011,
2019-05-22 07:42:24 +08:00
None = 0b100,
2019-05-21 08:53:59 +08:00
}
2019-05-24 00:23:51 +08:00
#[repr(u8)]
2019-05-22 07:42:24 +08:00
pub enum StopBits {
One = 0b00,
OneAndHalf = 0b01,
Two = 0b10,
}
2019-05-21 08:53:59 +08:00
#[repr(C)]
2019-05-05 20:56:23 +08:00
pub struct RegisterBlock {
2019-05-07 23:46:37 +08:00
pub control: Control,
pub mode: Mode,
pub intrpt_en: RW<u32>,
pub intrpt_dis: RW<u32>,
pub intrpt_mask: RO<u32>,
pub chnl_int_sts: WO<u32>,
pub baud_rate_gen: BaudRateGen,
pub rcvr_timeout: RW<u32>,
pub rcvr_fifo_trigger_level: RW<u32>,
pub modem_ctrl: RW<u32>,
pub modem_sts: RW<u32>,
pub channel_sts: ChannelSts,
pub tx_rx_fifo: TxRxFifo,
pub baud_rate_divider: BaudRateDiv,
pub flow_delay: RW<u32>,
pub unused0: RO<u32>,
pub unused1: RO<u32>,
pub tx_fifo_trigger_level: RW<u32>,
2019-05-05 20:56:23 +08:00
}
2019-05-21 05:01:50 +08:00
register_at!(RegisterBlock, 0xE0000000, uart0);
register_at!(RegisterBlock, 0xE0001000, uart1);
2019-05-05 20:56:23 +08:00
register!(control, Control, RW, u32);
2019-05-07 05:56:53 +08:00
register_bit!(control, rxrst, 0);
register_bit!(control, txrst, 1);
register_bit!(control, rxen, 2);
register_bit!(control, rxdis, 3);
register_bit!(control, txen, 4);
register_bit!(control, txdis, 5);
2019-05-21 07:30:54 +08:00
register_bit!(control, rstto, 6);
register_bit!(control, sttbrk, 7);
register_bit!(control, stpbrk, 8);
2019-05-07 05:56:53 +08:00
register!(mode, Mode, RW, u32);
2019-05-21 07:30:54 +08:00
/// Channel mode: Defines the mode of operation of the UART.
2019-05-24 00:23:51 +08:00
register_bits_typed!(mode, chmode, u8, ChannelMode, 8, 9);
2019-05-22 07:42:24 +08:00
/// Number of stop bits
2019-05-24 00:23:51 +08:00
register_bits_typed!(mode, nbstop, u8, StopBits, 6, 7);
2019-05-22 07:42:24 +08:00
/// Parity type select
2019-05-24 00:23:51 +08:00
register_bits_typed!(mode, par, u8, ParityMode, 3, 5);
2019-05-22 07:42:24 +08:00
/// Character length select
register_bits!(mode, chrl, u8, 1, 2);
/// Clock source select
register_bit!(mode, clks, 0);
2019-05-07 05:56:53 +08:00
register!(baud_rate_gen, BaudRateGen, RW, u32);
2019-05-07 05:56:53 +08:00
register_bits!(baud_rate_gen, cd, u16, 0, 15);
register!(channel_sts, ChannelSts, RO, u32);
/// Transmitter FIFO Nearly Full
register_bit!(channel_sts, tnful, 14);
/// Tx FIFO fill level is greater than or equal to TTRIG?
register_bit!(channel_sts, ttrig, 13);
/// Rx FIFO fill level is greater than or equal to FDEL?
register_bit!(channel_sts, flowdel, 12);
/// Transmitter state machine active?
register_bit!(channel_sts, tactive, 11);
/// Receiver state machine active?
register_bit!(channel_sts, ractive, 10);
/// Tx FIFO is full?
2019-05-07 05:56:53 +08:00
register_bit!(channel_sts, txfull, 4);
/// Tx FIFO is empty?
register_bit!(channel_sts, txempty, 3);
/// Rx FIFO is full?
register_bit!(channel_sts, rxfull, 2);
/// Rx FIFO is empty?
register_bit!(channel_sts, rxempty, 1);
/// Rx FIFO fill level is greater than or equal to RTRIG?
register_bit!(channel_sts, rxovr, 0);
2019-05-07 05:56:53 +08:00
register!(tx_rx_fifo, TxRxFifo, RW, u32);
2019-05-07 05:56:53 +08:00
register_bits!(tx_rx_fifo, data, u32, 0, 31);
register!(baud_rate_div, BaudRateDiv, RW, u32);
2019-05-07 05:56:53 +08:00
register_bits!(baud_rate_div, bdiv, u8, 0, 7);