2019-05-08 01:28:33 +08:00
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use crate::regs::*;
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mod regs;
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pub struct Eth {
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2019-05-24 00:01:18 +08:00
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regs: &'static mut regs::RegisterBlock,
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2019-05-08 01:28:33 +08:00
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}
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impl Eth {
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pub fn gem0() -> Self {
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let regs = unsafe { regs::RegisterBlock::gem0() };
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Eth { regs }.init()
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}
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pub fn gem1() -> Self {
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let regs = unsafe { regs::RegisterBlock::gem1() };
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Eth { regs }.init()
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}
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fn init(self) -> Self {
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed().clear_stat_regs(true));
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// Clear the Status registers.
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self.regs.rx_status.write(
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regs::RxStatus::zeroed()
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.buffer_not_avail(true)
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.frame_recd(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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);
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self.regs.tx_status.write(
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regs::TxStatus::zeroed()
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.used_bit_read(true)
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.collision(true)
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.retry_limit_exceeded(true)
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.tx_go(true)
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.tx_corr_ahb_err(true)
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.tx_complete(true)
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.tx_under_run(true)
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.late_collision(true)
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.hresp_not_ok(true)
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);
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// Disable all interrupts.
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.mgmt_done(true)
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.rx_complete(true)
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.rx_used_read(true)
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.tx_used_read(true)
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.tx_underrun(true)
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.retry_ex_late_collisn(true)
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.tx_corrupt_ahb_err(true)
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.tx_complete(true)
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.link_chng(true)
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.rx_overrun(true)
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.hresp_not_ok(true)
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.pause_nonzeroq(true)
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.pause_zero(true)
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.pause_tx(true)
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.ex_intr(true)
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.autoneg_complete(true)
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.partner_pg_rx(true)
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.delay_req_rx(true)
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.sync_rx(true)
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.delay_req_tx(true)
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.sync_tx(true)
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.pdelay_req_rx(true)
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.pdelay_resp_rx(true)
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.pdelay_req_tx(true)
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.pdelay_resp_tx(true)
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.tsu_sec_incr(true)
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);
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// Clear the buffer queues.
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self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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);
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self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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);
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self
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}
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}
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