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194 Commits

Author SHA1 Message Date
architeuthidae 2b829885ac Add makefile and .gitignore 2024-10-27 19:09:12 +01:00
architeuthidae c9b68e38b6 Add datasheet template.tex 2024-10-25 11:58:47 +08:00
architeuthidae ed02c0abe2 2218-2128: fix image imports 2024-10-24 22:59:12 +02:00
architeuthidae b7a9d08233 Standardize labels to preamble 2024-10-24 22:59:12 +02:00
architeuthidae c32b128d6f Unify preamble.tex, footnote.tex 2024-10-23 15:51:50 +02:00
architeuthidae a9674e90df Refactor images 2024-10-23 15:51:50 +02:00
mwojcik 3480a1a6d0 4410: fix SUServo DIP switch configuration 2024-08-06 18:53:07 +08:00
occheung f3858552b6 2245: remove absolute maximum specs 
Closes #50
 2022-09-05 11:55:31 +08:00
occheung ebc1235847 1124: add insn for clock configuation setup 2022-08-11 10:48:50 +08:00
occheung 4b9822c07e 1124: init 2022-08-09 17:31:27 +08:00
occheung d387006656 2118-2128: (max. -> min.) sustained event separation 2022-07-27 15:17:32 +08:00
occheung 69696899ac 2118-2128: tabulate MSES 2022-07-27 15:16:09 +08:00
occheung 8ce5cca85e 2118-2128: update code line range 2022-07-27 15:15:26 +08:00
occheung d6d29c89a1 ttl_in/MTD: fix time.sleep duration 2022-07-27 15:14:42 +08:00
occheung a7dfa03a21 ttl_in/MTD: import time 2022-07-27 15:14:12 +08:00
occheung 440b3ef3df 2118-2128: add t_min info from #26 2022-07-26 18:26:52 +08:00
occheung 7d993a4800 2238: remove min input edge rate 
Updates #48.
 2022-07-26 13:11:23 +08:00
occheung 77d31568b1 5108: specify noise in RMS 
Updates #52.
 2022-07-26 13:10:06 +08:00
occheung df564d2375 5108: remove gain condition for terminated voltage spec 2022-07-25 17:29:26 +08:00
occheung b8e89f4d01 4410/linearity: expected -> ideal 2022-07-25 17:01:03 +08:00
occheung 8138e793d7 7210: cite waveform plot 2022-07-25 16:33:42 +08:00
occheung a14aa89a76 7210: fix specs 
Replaced plot with the one produced by a faster scope (20 GSa/s).
 2022-07-25 16:25:26 +08:00
occheung 5d8dc38db7 7210: clarify on clock in/out format 2022-07-25 14:56:20 +08:00
occheung 688f5fdf23 7210: add phaser clock input to application 
Closes #42.
 2022-07-25 14:30:45 +08:00
occheung 3a6ed63f0a 2118-2128: add RTIO constraint 2022-07-22 17:46:35 +08:00
occheung c1388a53a8 4410: remove dead titles 2022-06-24 11:31:39 +08:00
occheung af0fca61e2 4410: replot voltage measured vs expected 2022-06-24 11:29:40 +08:00
occheung 6d9faa7bb9 4410: add asf vs v_rms 2022-06-23 16:58:16 +08:00
occheung 42cbd9e195 7210: init 2022-06-22 14:53:31 +08:00
occheung 2838213457 fix language 2022-06-17 16:12:27 +08:00
occheung 2d0a866274 2238: add spec on max voltage with term 
Updates #35.
Same termination structure as bnc/sma-ttl card.
Technically the max allowable voltage with termination is a bit higher than 5V.
But it seems that it will still exceed the termination resistor rating limit at 5.5V.
The only method of acquiring V_ds & other parameters is by eye-balling the I-V curve of the MOSFET, which is not precise.
So the calculation assumes V_ds=0, just to be conservative.
 2022-06-17 16:07:21 +08:00
occheung 2964e13102 2118-2128: separate term rating to another spec 2022-06-17 16:06:26 +08:00
occheung 1cf6919ec8 add missing plot in b476c178 2022-06-17 13:34:56 +08:00
occheung 5c44a65d33 5568: init 
There aren't any electrical specs, as suggested by the lack of electronic components.
There is a colored version of the connection diagram, but I think the B&W one actually looks better.
 2022-06-16 16:02:47 +08:00
occheung c1c078671b examples: move SPI examples to spi.py 2022-06-16 16:00:22 +08:00
occheung 9920661516 2245: add dio_spi examples 2022-06-13 17:27:32 +08:00
occheung 8ff606888c 2118-2128: add BNC-TTL front panels 2022-06-09 16:54:00 +08:00
occheung 8c2c9ecfe4 5108: mention possible SMA breakout option 
Updates #13
 2022-06-09 11:51:44 +08:00
occheung 11ee1ebcbd 5518-5528: init 2022-06-08 17:22:55 +08:00
occheung b86eea7611 4410-4412: remove mention of external sync signal distribution 
Updates #38
 2022-06-08 17:21:27 +08:00
occheung ac639b9d1e 2118-2128: add TTLClockGen example 2022-06-07 16:01:18 +08:00
occheung 9bd1412d9c 2118-2128: Add comment to make coarse RTIO cycle clear 2022-06-07 14:36:21 +08:00
occheung 2a5066ac5f 2118-2128: add <8ns short pulse example 2022-06-07 13:49:14 +08:00
occheung f5ce9e19e9 4410-4412: add eem mode docs 2022-06-07 12:46:23 +08:00
occheung fa0de2a72d 5108: add 'ADC' to title 2022-02-14 17:36:05 +08:00
occheung 2a9d7f4f9c 4456: clarify setup for the tests 2022-02-14 11:02:07 +08:00
occheung 75f3a328db 4456: dds -> pll 2022-02-14 10:38:28 +08:00
occheung b476c178d0 2118-2128: add min pulse width spec 
Especially test reuslt that validate the "minimum 3ns pulse width" claim.
 2022-02-08 13:33:55 +08:00
occheung 3ed6a7ccbe 2118-2128: fix data rate spec 
Quoted from the isolator datasheet: "Data rates up to 150 Mbps are supported."
Saying the maximum data rate is at least 150 Mbps is not very accurate.
Updates #36
 2022-02-07 14:41:09 +08:00
occheung d622423675 4456: remove mention to cpld cfg on rf_sw 
As communication to ALmazny mezzanine does not use bitbang anymore, there is very little value for routing LVDS signal.
Also, MUXOUT readout from ADF5356 has an easily understandable API available.
So there should not be any reasons to use EEM[4:8] for anything other than controlling RF switches.
 2022-02-07 14:28:07 +08:00