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migen: debug spi connection

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This commit is contained in:
occheung 2020-08-09 13:42:18 +08:00
parent 3793d6d67c
commit 393138dc9a
3 changed files with 26 additions and 25 deletions
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2
.cargo/config
View File

@ -1,5 +1,5 @@
[target.thumbv7em-none-eabihf] [target.thumbv7em-none-eabihf]
runner = "gdb -q -x gdb_config/fpga_config.gdb" runner = "gdb -q -x gdb_config/debug.gdb"
rustflags = [ rustflags = [
"-C", "link-arg=-Tlink.x", "-C", "link-arg=-Tlink.x",
] ]

3
migen/fpga_config.py
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@ -28,6 +28,9 @@ class UrukulConnector(Module):
eem.p[5].eq(spi.cs[2]), eem.p[5].eq(spi.cs[2]),
] ]
# Debug purposes: Tie MISO to MOSI
self.comb += spi.miso.eq(spi.mosi)
if __name__ == "__main__": if __name__ == "__main__":
platform = HumpbackPlatform() platform = HumpbackPlatform()

46
src/main.rs
View File

@ -49,38 +49,36 @@ fn main() -> ! {
Err(_) => hprintln!("Error: Cannot read C_DONE"), Err(_) => hprintln!("Error: Cannot read C_DONE"),
}.unwrap(); }.unwrap();
hprintln!("Start reading pin output...").unwrap(); /*
delay.delay_ms(200_u16); * Using SPI1, AF5
* SCLK -> PA5
* MOSI -> PB5
* MISO -> PA6
* CS -> 0: PB12, 1: PA15, 2: PC7
*/
let sclk = gpioa.pa5.into_alternate_af5();
let mosi = gpiob.pb5.into_alternate_af5();
let miso = gpioa.pa6.into_alternate_af5();
let pin = gpioa.pa0.into_pull_up_input(); let mut spi = dp.SPI1.spi(
let mut state = pin.is_high().unwrap(); (sclk, miso, mosi),
spi::MODE_0,
12.mhz(),
ccdr.peripheral.SPI1,
&ccdr.clocks,
);
hprintln!("Initial reading..."); let mut data :u8 = 0xAD;
match state {
true => hprintln!("High."),
false => hprintln!("Low."),
}.unwrap();
hprintln!("Polling...");
loop { loop {
if pin.is_high().unwrap() != state { hprintln!("Sent {}", data).unwrap();
match !state { block!(spi.send(data)).unwrap();
true => hprintln!("High."), data = block!(spi.read()).unwrap();
false => hprintln!("Low."), hprintln!("Read {}", data).unwrap();
}.unwrap();
state = !state;
}
if fpga_cdone.is_low().unwrap() {
hprintln!("FPGA is in reset state.");
} }
} }
}