From 393138dc9ab911a2abd350851892f8b320ff6326 Mon Sep 17 00:00:00 2001 From: occheung Date: Sun, 9 Aug 2020 13:42:18 +0800 Subject: [PATCH] migen: debug spi connection --- .cargo/config | 2 +- migen/fpga_config.py | 3 +++ src/main.rs | 46 +++++++++++++++++++++----------------------- 3 files changed, 26 insertions(+), 25 deletions(-) diff --git a/.cargo/config b/.cargo/config index c0ce242..6c91033 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = "gdb -q -x gdb_config/fpga_config.gdb" +runner = "gdb -q -x gdb_config/debug.gdb" rustflags = [ "-C", "link-arg=-Tlink.x", ] diff --git a/migen/fpga_config.py b/migen/fpga_config.py index 6d089d3..2eb8a15 100644 --- a/migen/fpga_config.py +++ b/migen/fpga_config.py @@ -28,6 +28,9 @@ class UrukulConnector(Module): eem.p[5].eq(spi.cs[2]), ] + # Debug purposes: Tie MISO to MOSI + self.comb += spi.miso.eq(spi.mosi) + if __name__ == "__main__": platform = HumpbackPlatform() diff --git a/src/main.rs b/src/main.rs index 4199063..93615b5 100644 --- a/src/main.rs +++ b/src/main.rs @@ -49,36 +49,34 @@ fn main() -> ! { Err(_) => hprintln!("Error: Cannot read C_DONE"), }.unwrap(); - hprintln!("Start reading pin output...").unwrap(); - delay.delay_ms(200_u16); + /* + * Using SPI1, AF5 + * SCLK -> PA5 + * MOSI -> PB5 + * MISO -> PA6 + * CS -> 0: PB12, 1: PA15, 2: PC7 + */ + let sclk = gpioa.pa5.into_alternate_af5(); + let mosi = gpiob.pb5.into_alternate_af5(); + let miso = gpioa.pa6.into_alternate_af5(); - let pin = gpioa.pa0.into_pull_up_input(); - let mut state = pin.is_high().unwrap(); + let mut spi = dp.SPI1.spi( + (sclk, miso, mosi), + spi::MODE_0, + 12.mhz(), + ccdr.peripheral.SPI1, + &ccdr.clocks, + ); - hprintln!("Initial reading..."); - - match state { - true => hprintln!("High."), - false => hprintln!("Low."), - }.unwrap(); - - hprintln!("Polling..."); + let mut data :u8 = 0xAD; loop { - if pin.is_high().unwrap() != state { - match !state { - true => hprintln!("High."), - false => hprintln!("Low."), - }.unwrap(); - state = !state; - } - - if fpga_cdone.is_low().unwrap() { - hprintln!("FPGA is in reset state."); - } + hprintln!("Sent {}", data).unwrap(); + block!(spi.send(data)).unwrap(); + data = block!(spi.read()).unwrap(); + hprintln!("Read {}", data).unwrap(); } - }