forked from M-Labs/humpback-dds
bitmask: add mask merging
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181ef5c72a
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5f874e81b5
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@ -1,3 +1,5 @@
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use core::mem::size_of;
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/*
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* Macro builder for bit masks
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* $collection: Name for the bit mask collection
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@ -33,7 +35,7 @@ macro_rules! construct_bitmask {
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pub(crate) fn get_bitmask(self) -> $unsigned_type {
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let mut mask: $unsigned_type = 0;
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for bit in 0..self.get_width() {
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mask |= (1 << (self.get_shift() + bit));
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mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
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}
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mask
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}
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@ -48,7 +50,7 @@ macro_rules! construct_bitmask {
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}
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pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
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// Filter everything then shift bits
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((data & self.get_bitmask()) >> self.get_shift())
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((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
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}
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}
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}
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@ -1,6 +1,7 @@
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use embedded_hal::blocking::spi::Transfer;
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use cortex_m_semihosting::hprintln;
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use crate::Error;
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use core::mem::size_of;
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// Bitmasks for CFG
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construct_bitmask!(CFGMask; u32;
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@ -81,7 +82,7 @@ where
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}
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/*
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* Return status
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* Return status using mask
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*/
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pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
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match self.set_all_configurations() {
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@ -89,6 +90,14 @@ where
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Err(e) => Err(e),
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}
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}
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/*
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* Return entire status register
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*/
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pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
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return self.set_all_configurations();
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}
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}
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impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
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69
src/dds.rs
69
src/dds.rs
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@ -1,8 +1,10 @@
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use embedded_hal::blocking::spi::Transfer;
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use cortex_m_semihosting::hprintln;
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use crate::Error;
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use core::mem::size_of;
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construct_bitmask!(CFR1Mask; u32;
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construct_bitmask!(DDSCFRMask; u32;
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// CFR1 bitmasks
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LSB_FIRST, 0, 1,
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SDIO_IN_ONLY, 1, 1,
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EXT_POWER_DOWN_CTRL, 3, 1,
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@ -23,38 +25,36 @@ construct_bitmask!(CFR1Mask; u32;
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INV_SINC_FILTER_ENABLE, 22, 1,
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MANUAL_OSK_EXT_CTRL, 23, 1,
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RAM_PLAYBACK_DST, 29, 2,
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RAM_ENABLE, 31, 1
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);
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RAM_ENABLE, 31, 1,
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construct_bitmask!(CFR2Mask; u32;
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FM_GAIN, 0, 4,
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PARALLEL_DATA_PORT_ENABLE, 4, 1,
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SYNC_TIM_VALIDATION_DISABLE, 5, 1,
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DATA_ASSEM_HOLD_LAST_VALUE, 6, 1,
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MATCHED_LATENCY_ENABLE, 7, 1,
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TXENABLE_INV, 9, 1,
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PDCLK_INV, 10, 1,
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PDCLK_ENABLE, 11, 1,
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IO_UPDATE_RATE_CTRL, 14, 2,
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READ_EFFECTIVE_FTW, 16, 1,
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DIGITAL_RAMP_NO_DWELL_LOW, 17, 1,
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DIGITAL_RAMP_NO_DWELL_HIGH, 18, 1,
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DIGITAL_RAMP_ENABLE, 19, 1,
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DIGITAL_RAMP_DEST, 20, 2,
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SYNC_CLK_ENABLE, 22, 1,
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INT_IO_UPDATE_ACTIVE, 23, 1,
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EN_AMP_SCALE_SINGLE_TONE_PRO, 24, 1
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);
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// CFR2 bitmasks
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FM_GAIN, 0 +32, 4,
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PARALLEL_DATA_PORT_ENABLE, 4 +32, 1,
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SYNC_TIM_VALIDATION_DISABLE, 5 +32, 1,
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DATA_ASSEM_HOLD_LAST_VALUE, 6 +32, 1,
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MATCHED_LATENCY_ENABLE, 7 +32, 1,
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TXENABLE_INV, 9 +32, 1,
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PDCLK_INV, 10 +32, 1,
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PDCLK_ENABLE, 11 +32, 1,
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IO_UPDATE_RATE_CTRL, 14 +32, 2,
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READ_EFFECTIVE_FTW, 16 +32, 1,
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DIGITAL_RAMP_NO_DWELL_LOW, 17 +32, 1,
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DIGITAL_RAMP_NO_DWELL_HIGH, 18 +32, 1,
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DIGITAL_RAMP_ENABLE, 19 +32, 1,
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DIGITAL_RAMP_DEST, 20 +32, 2,
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SYNC_CLK_ENABLE, 22 +32, 1,
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INT_IO_UPDATE_ACTIVE, 23 +32, 1,
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EN_AMP_SCALE_SINGLE_TONE_PRO, 24 +32, 1,
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construct_bitmask!(CFR3Mask; u32;
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N, 1, 7,
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PLL_ENABLE, 8, 1,
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PFD_RESET, 10, 1,
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REFCLK_IN_DIV_RESETB, 14, 1,
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REFCLK_IN_DIV_BYPASS, 15, 1,
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I_CP, 19, 3,
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VCO_SEL, 24, 3,
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DRV0, 28, 2
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// CFR3 bitmasks
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N, 1 +64, 7,
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PLL_ENABLE, 8 +64, 1,
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PFD_RESET, 10 +64, 1,
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REFCLK_IN_DIV_RESETB, 14 +64, 1,
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REFCLK_IN_DIV_BYPASS, 15 +64, 1,
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I_CP, 19 +64, 3,
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VCO_SEL, 24 +64, 3,
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DRV0, 28 +64, 2
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);
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const WRITE_MASK :u8 = 0x00;
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@ -86,6 +86,13 @@ where
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}
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}
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// impl<SPI, E> DDS<SPI>
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// where
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// SPI: Transfer<u8, Error = E>
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// {
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// pub fn set_configuration
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// }
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macro_rules! impl_register_io {
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($($reg_addr: expr, $reg_byte_size: expr),+) => {
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impl<SPI, E> DDS<SPI>
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