From 5f874e81b5275746f8cb938c3c3a6b41e99cab36 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Wed, 26 Aug 2020 11:04:08 +0800
Subject: [PATCH] bitmask: add mask merging

---
 src/bitmask_macro.rs   |  6 ++--
 src/config_register.rs | 11 ++++++-
 src/dds.rs             | 69 +++++++++++++++++++++++-------------------
 3 files changed, 52 insertions(+), 34 deletions(-)

diff --git a/src/bitmask_macro.rs b/src/bitmask_macro.rs
index 784c205..4836f44 100644
--- a/src/bitmask_macro.rs
+++ b/src/bitmask_macro.rs
@@ -1,3 +1,5 @@
+use core::mem::size_of;
+
 /*
  * Macro builder for bit masks
  * $collection: Name for the bit mask collection
@@ -33,7 +35,7 @@ macro_rules! construct_bitmask {
 			pub(crate) fn get_bitmask(self) -> $unsigned_type {
 				let mut mask: $unsigned_type = 0;
 				for bit in 0..self.get_width() {
-					mask |= (1 << (self.get_shift() + bit));
+					mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
 				}
 				mask
 			}
@@ -48,7 +50,7 @@ macro_rules! construct_bitmask {
 			}
 			pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
 				// Filter everything then shift bits
-				((data & self.get_bitmask()) >> self.get_shift())
+				((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
 			}
 		}
 	}
diff --git a/src/config_register.rs b/src/config_register.rs
index 6767d01..0f056ad 100644
--- a/src/config_register.rs
+++ b/src/config_register.rs
@@ -1,6 +1,7 @@
 use embedded_hal::blocking::spi::Transfer;
 use cortex_m_semihosting::hprintln;
 use crate::Error;
+use core::mem::size_of;
 
 // Bitmasks for CFG
 construct_bitmask!(CFGMask; u32;
@@ -81,7 +82,7 @@ where
 	}
 
 	/*
-	 * Return status
+	 * Return status using mask
 	 */
 	pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
 		match self.set_all_configurations() {
@@ -89,6 +90,14 @@ where
 			Err(e) => Err(e),
 		}
 	}
+
+	/*
+	 * Return entire status register
+	 */
+	pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
+		return self.set_all_configurations();
+	}
+	
 }
 
 impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>
diff --git a/src/dds.rs b/src/dds.rs
index 53f05a6..fb0abaf 100644
--- a/src/dds.rs
+++ b/src/dds.rs
@@ -1,8 +1,10 @@
 use embedded_hal::blocking::spi::Transfer;
 use cortex_m_semihosting::hprintln;
 use crate::Error;
+use core::mem::size_of;
 
-construct_bitmask!(CFR1Mask; u32;
+construct_bitmask!(DDSCFRMask; u32;
+	// CFR1 bitmasks
 	LSB_FIRST,						0,	1,
 	SDIO_IN_ONLY,					1,	1,
 	EXT_POWER_DOWN_CTRL,			3,	1,
@@ -23,38 +25,36 @@ construct_bitmask!(CFR1Mask; u32;
 	INV_SINC_FILTER_ENABLE,			22,	1,
 	MANUAL_OSK_EXT_CTRL,			23,	1,
 	RAM_PLAYBACK_DST,				29,	2,
-	RAM_ENABLE,						31,	1
-);
+	RAM_ENABLE,						31,	1,
 
-construct_bitmask!(CFR2Mask; u32;
-	FM_GAIN,						0,	4,
-	PARALLEL_DATA_PORT_ENABLE,		4,	1,
-	SYNC_TIM_VALIDATION_DISABLE,	5,	1,
-	DATA_ASSEM_HOLD_LAST_VALUE,		6,	1,
-	MATCHED_LATENCY_ENABLE,			7,	1,
-	TXENABLE_INV,					9,	1,
-	PDCLK_INV,						10,	1,
-	PDCLK_ENABLE,					11,	1,
-	IO_UPDATE_RATE_CTRL,			14,	2,
-	READ_EFFECTIVE_FTW,				16,	1,
-	DIGITAL_RAMP_NO_DWELL_LOW,		17,	1,
-	DIGITAL_RAMP_NO_DWELL_HIGH,		18,	1,
-	DIGITAL_RAMP_ENABLE,			19,	1,
-	DIGITAL_RAMP_DEST,				20,	2,
-	SYNC_CLK_ENABLE,				22,	1,	
-	INT_IO_UPDATE_ACTIVE,			23,	1,
-	EN_AMP_SCALE_SINGLE_TONE_PRO,	24,	1
-);
+	// CFR2 bitmasks
+	FM_GAIN,						0  +32,	4,
+	PARALLEL_DATA_PORT_ENABLE,		4  +32,	1,
+	SYNC_TIM_VALIDATION_DISABLE,	5  +32,	1,
+	DATA_ASSEM_HOLD_LAST_VALUE,		6  +32,	1,
+	MATCHED_LATENCY_ENABLE,			7  +32,	1,
+	TXENABLE_INV,					9  +32,	1,
+	PDCLK_INV,						10 +32,	1,
+	PDCLK_ENABLE,					11 +32,	1,
+	IO_UPDATE_RATE_CTRL,			14 +32,	2,
+	READ_EFFECTIVE_FTW,				16 +32,	1,
+	DIGITAL_RAMP_NO_DWELL_LOW,		17 +32,	1,
+	DIGITAL_RAMP_NO_DWELL_HIGH,		18 +32,	1,
+	DIGITAL_RAMP_ENABLE,			19 +32,	1,
+	DIGITAL_RAMP_DEST,				20 +32,	2,
+	SYNC_CLK_ENABLE,				22 +32,	1,	
+	INT_IO_UPDATE_ACTIVE,			23 +32,	1,
+	EN_AMP_SCALE_SINGLE_TONE_PRO,	24 +32,	1,
 
-construct_bitmask!(CFR3Mask; u32;
-	N,								1,	7,
-	PLL_ENABLE,						8,	1,
-	PFD_RESET,						10,	1,
-	REFCLK_IN_DIV_RESETB,			14,	1,
-	REFCLK_IN_DIV_BYPASS,			15,	1,
-	I_CP,							19,	3,
-	VCO_SEL,						24,	3,
-	DRV0,							28,	2
+	// CFR3 bitmasks
+	N,								1  +64,	7,
+	PLL_ENABLE,						8  +64,	1,
+	PFD_RESET,						10 +64,	1,
+	REFCLK_IN_DIV_RESETB,			14 +64,	1,
+	REFCLK_IN_DIV_BYPASS,			15 +64,	1,
+	I_CP,							19 +64,	3,
+	VCO_SEL,						24 +64,	3,
+	DRV0,							28 +64,	2
 );
 
 const WRITE_MASK 	:u8 = 0x00;
@@ -86,6 +86,13 @@ where
 	}
 }
 
+// impl<SPI, E> DDS<SPI>
+// where
+// 	SPI: Transfer<u8, Error = E>
+// {
+// 	pub fn set_configuration	
+// }
+
 macro_rules! impl_register_io {
 	($($reg_addr: expr, $reg_byte_size: expr),+) => {
 		impl<SPI, E> DDS<SPI>