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migen: fix comment

This commit is contained in:
occheung 2020-09-17 10:06:33 +08:00
parent 52b285742e
commit 4d73786880
1 changed files with 10 additions and 13 deletions
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23
migen/fpga_config.py
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@ -1,5 +1,4 @@
# from humpback import HumpbackPlatform # Import built in I/O, Connectors & Platform template for Humpback
# Import built in I/O, Connectors & Platform template
from migen.build.platforms.sinara import humpback from migen.build.platforms.sinara import humpback
# Import migen platform for Lattice Products # Import migen platform for Lattice Products
from migen.build.lattice import LatticePlatform from migen.build.lattice import LatticePlatform
@ -7,11 +6,16 @@ from migen.build.lattice import LatticePlatform
from migen.build.generic_platform import * from migen.build.generic_platform import *
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.fhdl.specials import Instance from migen.fhdl.specials import Instance
from migen.fhdl.bitcontainer import value_bits_sign
from migen.genlib.io import * from migen.genlib.io import *
from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
from migen.genlib.io import DifferentialInput from migen.genlib.io import DifferentialInput
spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
io_update = [
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
]
class UrukulConnector(Module): class UrukulConnector(Module):
def __init__(self, platform): def __init__(self, platform):
@ -19,6 +23,8 @@ class UrukulConnector(Module):
eem0 = [ eem0 = [
platform.request("eem0", 0), platform.request("eem0", 0),
platform.request("eem0", 1), platform.request("eem0", 1),
# Supply EEM pin with negative polarity
# See issue/PR: https://github.com/m-labs/migen/pull/181
platform.request("eem0_n", 2), platform.request("eem0_n", 2),
platform.request("eem0", 3), platform.request("eem0", 3),
platform.request("eem0", 4), platform.request("eem0", 4),
@ -36,10 +42,7 @@ class UrukulConnector(Module):
assert len(spi_cs) == 3 assert len(spi_cs) == 3
assert len(io_update) == 1 assert len(io_update) == 1
# TODO: Assert EEM resources # Flip negative input to positive output
assert isinstance(eem0, list)
# Flip positive signal as negative output, maybe only do it for FPGA outputs
self.miso_n = Signal() self.miso_n = Signal()
# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead # Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
@ -78,12 +81,6 @@ class UrukulConnector(Module):
if __name__ == "__main__": if __name__ == "__main__":
spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
io_update = [
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
]
platform = humpback.Platform() platform = humpback.Platform()
platform.add_extension(spi_cs) platform.add_extension(spi_cs)
platform.add_extension(io_update) platform.add_extension(io_update)