From 4d73786880eec8562f8dbe095177d5dc2dfa851c Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Thu, 17 Sep 2020 10:06:33 +0800
Subject: [PATCH] migen: fix comment

---
 migen/fpga_config.py | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index 86d9e9f..20fb3d6 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -1,5 +1,4 @@
-# from humpback import HumpbackPlatform
-# Import built in I/O, Connectors & Platform template
+# Import built in I/O, Connectors & Platform template for Humpback
 from migen.build.platforms.sinara import humpback
 # Import migen platform for Lattice Products
 from migen.build.lattice import LatticePlatform
@@ -7,11 +6,16 @@ from migen.build.lattice import LatticePlatform
 from migen.build.generic_platform import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance
-from migen.fhdl.bitcontainer import value_bits_sign
 from migen.genlib.io import *
 from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
 from migen.genlib.io import DifferentialInput
 
+spi_cs = [
+	("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
+]
+io_update = [
+	("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
+]
 
 class UrukulConnector(Module):
 	def __init__(self, platform):
@@ -19,6 +23,8 @@ class UrukulConnector(Module):
 		eem0 = [
 			platform.request("eem0", 0),
 			platform.request("eem0", 1),
+			# Supply EEM pin with negative polarity
+			# See issue/PR: https://github.com/m-labs/migen/pull/181
 			platform.request("eem0_n", 2),
 			platform.request("eem0", 3),
 			platform.request("eem0", 4),
@@ -36,10 +42,7 @@ class UrukulConnector(Module):
 		assert len(spi_cs) == 3
 		assert len(io_update) == 1
 
-		# TODO: Assert EEM resources
-		assert isinstance(eem0, list)
-
-		# Flip positive signal as negative output, maybe only do it for FPGA outputs
+		# Flip negative input to positive output
 		self.miso_n = Signal()
 
 		# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
@@ -78,12 +81,6 @@ class UrukulConnector(Module):
 
 
 if __name__ == "__main__":
-	spi_cs = [
-		("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
-	]
-	io_update = [
-		("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
-	]
 	platform = humpback.Platform()
 	platform.add_extension(spi_cs)
 	platform.add_extension(io_update)