forked from M-Labs/humpback-dds
dds: add clock control
This commit is contained in:
parent
38b1c7528c
commit
1d3ced0d16
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@ -1,5 +1,4 @@
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use embedded_hal::blocking::spi::Transfer;
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use embedded_hal::blocking::spi::Transfer;
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use cortex_m::asm::nop;
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use cortex_m_semihosting::hprintln;
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use cortex_m_semihosting::hprintln;
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use core::assert;
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use core::assert;
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@ -1,5 +1,3 @@
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use core::mem::size_of;
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/*
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/*
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* Macro builder for bit masks
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* Macro builder for bit masks
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* $collection: Name for the bit mask collection
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* $collection: Name for the bit mask collection
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@ -78,7 +78,7 @@ where
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* Return selected configuration field
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* Return selected configuration field
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*/
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*/
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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(config_type.get_filtered_content(self.data) as u8)
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config_type.get_filtered_content(self.data) as u8
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}
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}
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/*
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/*
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95
src/dds.rs
95
src/dds.rs
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@ -65,15 +65,17 @@ const READ_MASK :u8 = 0x80;
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pub struct DDS<SPI> {
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pub struct DDS<SPI> {
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spi: SPI,
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spi: SPI,
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f_ref_clk: u64,
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}
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}
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impl<SPI, E> DDS<SPI>
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impl<SPI, E> DDS<SPI>
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where
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where
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SPI: Transfer<u8, Error = E>
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SPI: Transfer<u8, Error = E>
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{
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{
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pub fn new(spi: SPI) -> Self {
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pub fn new(spi: SPI, f_ref_clk: u64) -> Self {
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DDS {
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DDS {
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spi
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spi,
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f_ref_clk,
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}
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}
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}
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}
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}
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}
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@ -89,13 +91,14 @@ where
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}
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}
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}
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}
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/*
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* Implement init
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*/
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impl<SPI, E> DDS<SPI>
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impl<SPI, E> DDS<SPI>
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where
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where
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SPI: Transfer<u8, Error = E>
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SPI: Transfer<u8, Error = E>
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{
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{
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/*
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* Implement init: Set SDIO to be input only, using LSB first
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*/
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pub fn init(&mut self) -> Result<(), Error<E>> {
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pub fn init(&mut self) -> Result<(), Error<E>> {
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match self.write_register(0x00, &mut [
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match self.write_register(0x00, &mut [
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0x00, 0x00, 0x00, 0x02
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0x00, 0x00, 0x00, 0x02
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@ -104,17 +107,81 @@ where
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Err(e) => Err(e),
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Err(e) => Err(e),
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}
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}
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}
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}
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/*
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* Implement clock control
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*/
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pub fn enable_divided_ref_clk(&mut self) -> Result<(), Error<E>> {
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self.set_configurations(&mut [
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// Disable PLL
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(DDSCFRMask::PLL_ENABLE, 0),
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// Take ref_clk source from divider
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 0),
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// Ensure divider is not reset
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(DDSCFRMask::REFCLK_IN_DIV_RESETB, 1),
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])
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}
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pub fn enable_normal_ref_clk(&mut self) -> Result<(), Error<E>> {
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self.set_configurations(&mut [
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// Disable PLL
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(DDSCFRMask::PLL_ENABLE, 0),
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// Take ref_clk source from divider bypass
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 1),
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// Reset does not matter
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(DDSCFRMask::REFCLK_IN_DIV_RESETB, 1),
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])
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}
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pub fn enable_pll(&mut self, f_sys_clk: u64) -> Result<(), Error<E>> {
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// Get a divider
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let divider = f_sys_clk / self.f_ref_clk;
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// Reject extreme divider values. However, accept no frequency division
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if ((divider > 127 || divider < 12) && divider != 1) {
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panic!("Invalid divider value for PLL!");
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}
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// Select a VCO
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let vco = if divider == 1 {
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6 // Bypass PLL if no frequency division needed
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} else if f_sys_clk > 1_150_000_000 {
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panic!("Invalid divider value for PLL!")
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} else if f_sys_clk > 820_000_000 {
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5
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} else if f_sys_clk > 700_000_000 {
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4
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} else if f_sys_clk > 600_000_000 {
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3
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} else if f_sys_clk > 500_000_000 {
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2
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} else if f_sys_clk > 420_000_000 {
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1
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} else if f_sys_clk > 370_000_000 {
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0
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} else {
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7 // Bypass PLL if f_sys_clk is too low
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};
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self.set_configurations(&mut [
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// Enable PLL, set divider (valid or not) and VCO
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(DDSCFRMask::PLL_ENABLE, 1),
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(DDSCFRMask::N, divider as u32),
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(DDSCFRMask::VCO_SEL, vco),
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// Reset PLL lock before re-enabling it
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(DDSCFRMask::PFD_RESET, 1),
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])?;
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self.set_configurations(&mut [
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(DDSCFRMask::PFD_RESET, 0),
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])
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}
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// Change external clock source (ref_clk)
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: u64) {
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self.f_ref_clk = f_ref_clk;
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}
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}
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/*
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/*
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* Impleement configurations registers I/O through bitmasks
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* Impleement configurations registers I/O through bitmasks
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*/
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*
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impl<SPI, E> DDS<SPI>
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* Get all (cfr1, cfr2, cfr3) contents
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where
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SPI: Transfer<u8, Error = E>
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{
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/*
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* Return (cfr1, cfr2, cfr3) contents
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*/
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*/
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fn get_all_configurations(&mut self) -> Result<[u32; 3], Error<E>> {
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fn get_all_configurations(&mut self) -> Result<[u32; 3], Error<E>> {
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let mut cfr_reg = [0; 12];
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let mut cfr_reg = [0; 12];
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@ -164,9 +231,8 @@ where
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*/
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*/
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pub fn set_configurations(&mut self, mask_pairs: &mut[(DDSCFRMask, u32)]) -> Result<(), Error<E>> {
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pub fn set_configurations(&mut self, mask_pairs: &mut[(DDSCFRMask, u32)]) -> Result<(), Error<E>> {
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let mut data_array = self.get_all_configurations()?;
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let mut data_array = self.get_all_configurations()?;
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hprintln!("Initial array {:#X?}", data_array).unwrap();
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for index in 0..mask_pairs.len() {
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for index in 0..mask_pairs.len() {
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// Reject any attempt to write LSB_FIRST and SBIO_INPUT_ONLY
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// Reject any attempt to rewrite LSB_FIRST and SBIO_INPUT_ONLY
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if mask_pairs[index].0 == DDSCFRMask::LSB_FIRST || mask_pairs[index].0 == DDSCFRMask::SDIO_IN_ONLY {
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if mask_pairs[index].0 == DDSCFRMask::LSB_FIRST || mask_pairs[index].0 == DDSCFRMask::SDIO_IN_ONLY {
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continue;
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continue;
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}
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}
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@ -177,7 +243,6 @@ where
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_ => panic!("Invalid DDSCFRMask!"),
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_ => panic!("Invalid DDSCFRMask!"),
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};
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};
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}
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}
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hprintln!("Modified array {:#X?}", data_array).unwrap();
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self.set_all_configurations(data_array.clone())
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self.set_all_configurations(data_array.clone())
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}
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}
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@ -6,10 +6,8 @@ use embedded_hal::{
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};
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};
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use core::cell;
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use core::cell;
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use core::mem::size_of;
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use cortex_m;
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_semihosting::hprintln;
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use cortex_m_semihosting::hprintln;
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#[macro_use]
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#[macro_use]
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40
src/main.rs
40
src/main.rs
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@ -10,13 +10,9 @@ use stm32h7xx_hal::hal::digital::v2::{
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use cortex_m;
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use cortex_m_semihosting::hprintln;
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use cortex_m_semihosting::hprintln;
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use core::ptr;
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use nb::block;
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use firmware;
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use firmware;
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use firmware::{
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use firmware::{
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CPLD,
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CPLD,
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@ -102,7 +98,7 @@ fn main() -> ! {
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let mut config = ConfigRegister::new(parts.spi1);
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let mut config = ConfigRegister::new(parts.spi1);
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let mut att = Attenuator::new(parts.spi2);
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let mut att = Attenuator::new(parts.spi2);
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let mut dds0 = DDS::new(parts.spi4);
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let mut dds0 = DDS::new(parts.spi4, 25_000_000);
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// Reset all DDS, set CLK_SEL to 0
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// Reset all DDS, set CLK_SEL to 0
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config.set_configurations(&mut [
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config.set_configurations(&mut [
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(CFGMask::IO_RST, 0),
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(CFGMask::IO_RST, 0),
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(CFGMask::RST, 0),
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(CFGMask::RST, 0),
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(CFGMask::RF_SW, 13),
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(CFGMask::RF_SW, 13),
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(CFGMask::DIV, 2)
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(CFGMask::DIV, 3)
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]).unwrap();
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]).unwrap();
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// dds0.write_register(0x00, &mut[
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// 0x00, 0x00, 0x00, 0x02
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// ]).unwrap();
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// dds0.write_register(0x01, &mut[
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// 0x01, 0x01, 0x00, 0x20
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// ]).unwrap();
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// dds0.write_register(0x02, &mut[
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// 0x05, 0x38, 0xC5, 0x28
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// ]).unwrap();
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dds0.init().unwrap();
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dds0.init().unwrap();
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dds0.set_configurations(&mut [
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dds0.set_configurations(&mut [
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@ -137,30 +121,17 @@ fn main() -> ! {
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(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
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(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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(DDSCFRMask::N, 0x14),
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(DDSCFRMask::PLL_ENABLE, 1),
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(DDSCFRMask::PFD_RESET, 1),
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 1),
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(DDSCFRMask::I_CP, 7),
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(DDSCFRMask::VCO_SEL, 5),
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(DDSCFRMask::DRV0, 0),
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]).unwrap();
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]).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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dds0.enable_pll(1_150_000_000).unwrap();
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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dds0.set_configurations(&mut [
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(DDSCFRMask::PFD_RESET, 0),
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]).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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0x00, 0x00, 0x00, 0x00
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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]).unwrap()).unwrap();
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// Calculate FTW
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// Calculate FTW
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let f_out = 8_008_135;
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let f_out = 10_000_000;
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let f_sclk = 100_000_000 / 2 * 20;
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let f_sclk = 1_150_000_000;
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let resolution :u64 = 1 << 32;
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let resolution :u64 = 1 << 32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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@ -177,6 +148,7 @@ fn main() -> ! {
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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dds0.write_register(0x0E, &mut profile).unwrap();
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dds0.write_register(0x0E, &mut profile).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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// Attenuator
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// Attenuator
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att.set_attenuation([
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att.set_attenuation([
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