forked from M-Labs/humpback-dds
dds: add register io
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parent
990fc075f1
commit
38b1c7528c
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@ -1,5 +1,5 @@
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[target.thumbv7em-none-eabihf]
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runner = "gdb -q -x gdb_config/openocd.gdb"
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runner = "gdb -q -x gdb_config/fpga_config.gdb"
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rustflags = [
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"-C", "link-arg=-Tlink.x",
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]
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@ -10,7 +10,7 @@ use core::mem::size_of;
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macro_rules! construct_bitmask {
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($collection: ident; $unsigned_type: ty; $($name: ident, $shift: expr, $width: expr),+) => {
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#[derive(Debug, Copy, Clone)]
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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pub enum $collection {
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$(
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$name,
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@ -41,7 +41,7 @@ macro_rules! construct_bitmask {
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}
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pub(crate) fn get_shifted_bits(self, arg: $unsigned_type) -> $unsigned_type {
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assert!(arg < (2 << self.get_width()));
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(arg << self.get_shift())
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(arg << (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
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}
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pub(crate) fn set_data_by_arg(self, data: &mut $unsigned_type, arg: $unsigned_type) {
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// Clear bits in field, then insert shifted argument
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102
src/dds.rs
102
src/dds.rs
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@ -3,6 +3,9 @@ use cortex_m_semihosting::hprintln;
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use crate::Error;
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use core::mem::size_of;
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/*
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* Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
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*/
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construct_bitmask!(DDSCFRMask; u32;
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// CFR1 bitmasks
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LSB_FIRST, 0, 1,
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@ -86,12 +89,99 @@ where
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}
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}
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// impl<SPI, E> DDS<SPI>
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// where
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// SPI: Transfer<u8, Error = E>
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// {
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// pub fn set_configuration
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// }
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/*
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* Implement init
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*/
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impl<SPI, E> DDS<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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pub fn init(&mut self) -> Result<(), Error<E>> {
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match self.write_register(0x00, &mut [
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0x00, 0x00, 0x00, 0x02
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]) {
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Ok(_) => Ok(()),
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Err(e) => Err(e),
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}
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}
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}
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/*
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* Impleement configurations registers I/O through bitmasks
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*/
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impl<SPI, E> DDS<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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/*
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* Return (cfr1, cfr2, cfr3) contents
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*/
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fn get_all_configurations(&mut self) -> Result<[u32; 3], Error<E>> {
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let mut cfr_reg = [0; 12];
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self.read_register(0x00, &mut cfr_reg[0..4])?;
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self.read_register(0x01, &mut cfr_reg[4..8])?;
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self.read_register(0x02, &mut cfr_reg[8..12])?;
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Ok([
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(cfr_reg[0] as u32) << 24 | (cfr_reg[1] as u32) << 16 | (cfr_reg[2] as u32) << 8 | (cfr_reg[3] as u32),
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(cfr_reg[4] as u32) << 24 | (cfr_reg[5] as u32) << 16 | (cfr_reg[6] as u32) << 8 | (cfr_reg[7] as u32),
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(cfr_reg[8] as u32) << 24 | (cfr_reg[9] as u32) << 16 | (cfr_reg[10] as u32) << 8 | (cfr_reg[11] as u32)
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])
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}
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/*
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* Get a set of configurations using DDSCFRMask
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*/
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pub fn get_configurations<'w>(&mut self, mask_pairs: &'w mut[(DDSCFRMask, u32)]) -> Result<&'w [(DDSCFRMask, u32)], Error<E>> {
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let data_array = self.get_all_configurations()?;
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for index in 0..mask_pairs.len() {
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mask_pairs[index].1 = match mask_pairs[index].0.get_shift() {
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0..=31 => mask_pairs[index].0.get_filtered_content(data_array[0]),
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32..=63 => mask_pairs[index].0.get_filtered_content(data_array[1]),
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64..=95 => mask_pairs[index].0.get_filtered_content(data_array[2]),
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_ => panic!("Invalid DDSCFRMask!"),
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}
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}
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Ok(mask_pairs)
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}
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/*
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* Write (cfr1, cfr2, cfr3) contents
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*/
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fn set_all_configurations(&mut self, data_array: [u32; 3]) -> Result<(), Error<E>> {
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for register in 0x00..=0x02 {
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self.write_register(register, &mut [
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((data_array[register as usize] >> 24) & 0xFF) as u8,
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((data_array[register as usize] >> 16) & 0xFF) as u8,
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((data_array[register as usize] >> 8 ) & 0xFF) as u8,
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((data_array[register as usize] >> 0 ) & 0xFF) as u8
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])?;
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}
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Ok(())
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}
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/*
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* Set a set of configurations using DDSCFRMask
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*/
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pub fn set_configurations(&mut self, mask_pairs: &mut[(DDSCFRMask, u32)]) -> Result<(), Error<E>> {
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let mut data_array = self.get_all_configurations()?;
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hprintln!("Initial array {:#X?}", data_array).unwrap();
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for index in 0..mask_pairs.len() {
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// Reject any attempt to write LSB_FIRST and SBIO_INPUT_ONLY
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if mask_pairs[index].0 == DDSCFRMask::LSB_FIRST || mask_pairs[index].0 == DDSCFRMask::SDIO_IN_ONLY {
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continue;
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}
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match mask_pairs[index].0.get_shift() {
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0..=31 => mask_pairs[index].0.set_data_by_arg(&mut data_array[0], mask_pairs[index].1),
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32..=63 => mask_pairs[index].0.set_data_by_arg(&mut data_array[1], mask_pairs[index].1),
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64..=95 => mask_pairs[index].0.set_data_by_arg(&mut data_array[2], mask_pairs[index].1),
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_ => panic!("Invalid DDSCFRMask!"),
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};
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}
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hprintln!("Modified array {:#X?}", data_array).unwrap();
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self.set_all_configurations(data_array.clone())
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}
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}
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macro_rules! impl_register_io {
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($($reg_addr: expr, $reg_byte_size: expr),+) => {
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@ -32,6 +32,7 @@ pub enum Error<E> {
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GetRefMutDataError,
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AttenuatorError,
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IOUpdateError,
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DDSError,
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}
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/*
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85
src/main.rs
85
src/main.rs
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@ -26,7 +26,10 @@ use firmware::{
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CFGMask,
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StatusMask,
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},
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dds::DDS,
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dds::{
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DDS,
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DDSCFRMask,
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},
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};
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#[entry]
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@ -94,7 +97,7 @@ fn main() -> ! {
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&ccdr.clocks,
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);
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let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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let mut config = ConfigRegister::new(parts.spi1);
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@ -111,35 +114,63 @@ fn main() -> ! {
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config.set_configurations(&mut [
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(CFGMask::IO_RST, 0),
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(CFGMask::RST, 0),
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(CFGMask::RF_SW, 1)
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(CFGMask::RF_SW, 13),
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(CFGMask::DIV, 2)
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]).unwrap();
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dds0.write_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x02
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// dds0.write_register(0x00, &mut[
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// 0x00, 0x00, 0x00, 0x02
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// ]).unwrap();
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// dds0.write_register(0x01, &mut[
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// 0x01, 0x01, 0x00, 0x20
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// ]).unwrap();
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// dds0.write_register(0x02, &mut[
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// 0x05, 0x38, 0xC5, 0x28
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// ]).unwrap();
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dds0.init().unwrap();
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dds0.set_configurations(&mut [
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(DDSCFRMask::PDCLK_ENABLE, 0),
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(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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(DDSCFRMask::N, 0x14),
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(DDSCFRMask::PLL_ENABLE, 1),
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(DDSCFRMask::PFD_RESET, 1),
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 1),
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(DDSCFRMask::I_CP, 7),
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(DDSCFRMask::VCO_SEL, 5),
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(DDSCFRMask::DRV0, 0),
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]).unwrap();
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dds0.write_register(0x02, &mut[
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0x01F, 0x3F, 0x41, 0x00
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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dds0.set_configurations(&mut [
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(DDSCFRMask::PFD_RESET, 0),
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]).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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// Calculate FTW
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let f_out = 10_000_000;
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let f_sclk = 100_000_000;
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let f_out = 8_008_135;
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let f_sclk = 100_000_000 / 2 * 20;
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let resolution :u64 = 1 << 32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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hprintln!("{}", ftw);
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// Read single-tone profile 0
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let mut profile :[u8; 8] = [0; 8];
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dds0.read_register(0x0E, &mut profile).unwrap();
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// Overwrite FTW on profile
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profile[0] = 0x20;
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// Overwrite FTW on profile 0
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profile[0] = 0x1F;
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profile[1] = 0xFF;
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profile[4] = ((ftw >> 24) & 0xFF) as u8;
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profile[5] = ((ftw >> 16) & 0xFF) as u8;
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profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
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@ -147,28 +178,22 @@ fn main() -> ! {
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dds0.write_register(0x0E, &mut profile).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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// Attenuator
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att.set_attenuation([
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0.0, 31.5, 24.0, 0.0
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]).unwrap();
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hprintln!("{:#X?}", att.get_attenuation().unwrap()).unwrap();
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hprintln!("{:#X?}", dds0.get_configurations(&mut
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[
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(DDSCFRMask::SDIO_IN_ONLY, 0),
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(DDSCFRMask::LSB_FIRST, 0),
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(DDSCFRMask::PROFILE_CTRL, 0),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 0),
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(DDSCFRMask::DRV0, 0),
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(DDSCFRMask::VCO_SEL, 0)
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]
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).unwrap()).unwrap();
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/*
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// Write to FTW register
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dds0.write_register(0x07, &mut [
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((ftw >> 24) & 0xFF) as u8,
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((ftw >> 16) & 0xFF) as u8,
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((ftw >> 8 ) & 0xFF) as u8,
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((ftw >> 0 ) & 0xFF) as u8,
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]).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x07, &mut [
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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*/
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loop {}
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}
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