151 lines
4.2 KiB
Rust
151 lines
4.2 KiB
Rust
//! ARM Generic Interrupt Controller
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use bit_field::BitField;
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use libregister::{RegisterW, RegisterRW, RegisterR};
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use super::mpcore;
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#[derive(Debug, Clone, Copy)]
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pub struct InterruptId(pub u8);
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#[derive(Debug, Clone, Copy)]
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#[repr(u8)]
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pub enum CPUCore {
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Core0 = 0b01,
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Core1 = 0b10
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}
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#[derive(Debug, Clone, Copy)]
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pub struct TargetCPU(u8);
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impl TargetCPU {
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pub const fn none() -> TargetCPU {
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TargetCPU(0)
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}
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pub const fn and(self, other: TargetCPU) -> TargetCPU {
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TargetCPU(self.0 | other.0)
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}
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}
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impl From<CPUCore> for TargetCPU {
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fn from(core: CPUCore) -> Self {
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TargetCPU(core as u8)
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}
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}
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pub enum TargetList {
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CPUList(TargetCPU),
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Others,
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This
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}
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impl From<CPUCore> for TargetList {
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fn from(core: CPUCore) -> Self {
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TargetList::CPUList(TargetCPU(core as u8))
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}
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}
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impl From<TargetCPU> for TargetList {
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fn from(cpu: TargetCPU) -> Self {
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TargetList::CPUList(cpu)
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}
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}
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#[derive(Debug, Clone, Copy)]
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pub enum InterruptSensitivity {
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Level,
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Edge,
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}
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pub struct InterruptController {
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mpcore: &'static mut mpcore::RegisterBlock,
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}
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impl InterruptController {
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pub fn gic(mpcore: &'static mut mpcore::RegisterBlock) -> Self {
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InterruptController { mpcore }
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}
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pub fn disable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(false)
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.enable_s(false));
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// FIXME: Should we disable the distributor globally when we disable interrupt (for a single
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// core)?
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// self.mpcore.icddcr.modify(|_, w| w.enable_secure(false)
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// .enable_non_secure(false));
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}
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/// enable interrupt signaling
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pub fn enable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(true)
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.enable_s(true));
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self.mpcore.icddcr.modify(|_, w| w.enable_secure(true));
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// Enable all interrupts except those of the lowest priority.
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self.mpcore.iccpmr.write(mpcore::ICCPMR::zeroed().priority(0xFF));
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}
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/// send software generated interrupt
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pub fn send_sgi(&mut self, id: InterruptId, targets: TargetList) {
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assert!(id.0 < 16);
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self.mpcore.icdsgir.modify(|_, w| match targets {
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TargetList::CPUList(list) => w.target_list_filter(0).cpu_target_list(list.0),
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TargetList::Others => w.target_list_filter(0b01),
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TargetList::This => w.target_list_filter(0b10)
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}.sgiintid(id.0).satt(false));
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}
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/// enable the interrupt *for this core*.
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/// Not needed for SGI.
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pub fn enable(&mut self, id: InterruptId, target_cpu: CPUCore, sensitivity: InterruptSensitivity, priority: u8) {
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// only 5 bits of the priority is useful
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assert!(priority < 32);
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self.disable_interrupts();
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// enable
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let m = (id.0 >> 5) as usize;
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let n = (id.0 & 0x1F) as usize;
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assert!(m < 3);
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unsafe {
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self.mpcore.icdiser[m].modify(|mut icdiser| *icdiser.set_bit(n, true));
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}
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// target cpu
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let m = (id.0 >> 2) as usize;
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let n = (8 * (id.0 & 3)) as usize;
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unsafe {
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self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1));
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}
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// sensitivity
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let m = (id.0 >> 4) as usize;
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let n = (2 * (id.0 & 0xF)) as usize;
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unsafe {
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self.mpcore.icdicfr[m].modify(|mut icdicfr| *icdicfr.set_bits(n..=n+1, match sensitivity {
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InterruptSensitivity::Level => 0b00,
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InterruptSensitivity::Edge => 0b10,
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}));
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}
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// priority
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let offset = (id.0 % 4) * 8;
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let priority: u32 = (priority as u32) << (offset + 3);
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let mask: u32 = 0xFFFFFFFF ^ (0xFF << offset);
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unsafe {
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self.mpcore.icdipr[id.0 as usize / 4].modify(|v| (v & mask) | priority);
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}
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self.enable_interrupts();
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}
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pub fn end_interrupt(&mut self, id: InterruptId) {
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self.mpcore.icceoir.modify(|_, w| w.eoiintid(id.0 as u32));
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}
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pub fn get_interrupt_id(&self) -> InterruptId {
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InterruptId(self.mpcore.icciar.read().ackintid() as u8)
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}
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}
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