334 lines
15 KiB
Rust
334 lines
15 KiB
Rust
use libregister::{register, register_at, register_bit, register_bits, RegisterRW, RegisterR, RegisterW};
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use super::asm::dmb;
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use volatile_register::RW;
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/// enable L2 cache with specific prefetch offset
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/// prefetch offset requires manual tuning, it seems that 8 is good for ZC706 current settings
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pub fn enable_l2_cache(offset: u8) {
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dmb();
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let regs = RegisterBlock::new();
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// disable L2 cache
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regs.reg1_control.modify(|_, w| w.l2_enable(false));
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regs.reg15_prefetch_ctrl.modify(|_, w|
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w.instr_prefetch_en(true)
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.data_prefetch_en(true)
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.double_linefill_en(true)
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.incr_double_linefill_en(true)
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.pref_drop_en(true)
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.prefetch_offset(offset)
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);
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regs.reg1_aux_control.modify(|_, w| {
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w.early_bresp_en(true)
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.instr_prefetch_en(true)
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.data_prefetch_en(true)
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.cache_replace_policy(true)
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.way_size(3)
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});
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regs.reg1_tag_ram_control.modify(|_, w| w.ram_wr_access_lat(1).ram_rd_access_lat(1).ram_setup_lat(1));
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regs.reg1_data_ram_control.modify(|_, w| w.ram_wr_access_lat(1).ram_rd_access_lat(2).ram_setup_lat(1));
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// invalidate L2 ways
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unsafe {
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regs.reg7_inv_way.write(0xFFFF);
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}
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// poll for completion
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while regs.reg7_cache_sync.read().c() {}
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// write to a magic memory location with a magic sequence
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// required in UG585 Section 3.4.10 Initialization Sequence
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unsafe {
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core::ptr::write_volatile(0xF8000008usize as *mut u32, 0xDF0D);
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core::ptr::write_volatile(0xF8000A1Cusize as *mut u32, 0x020202);
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core::ptr::write_volatile(0xF8000004usize as *mut u32, 0x767B);
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}
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regs.reg1_control.modify(|_, w| w.l2_enable(true));
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dmb();
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}
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#[inline(always)]
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pub fn l2_cache_invalidate_all() {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_inv_way.write(0xFFFF);
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}
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// poll for completion
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while regs.reg7_cache_sync.read().c() {}
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}
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#[inline(always)]
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pub fn l2_cache_clean_all() {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_clean_way.write(0xFFFF);
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}
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// poll for completion
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while regs.reg7_cache_sync.read().c() {}
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}
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#[inline(always)]
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pub fn l2_cache_clean_invalidate_all() {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_clean_inv_way.write(0xFFFF);
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}
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// poll for completion
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while regs.reg7_cache_sync.read().c() {}
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}
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/// L2 cache sync, similar to dsb for L1 cache
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#[inline(always)]
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pub fn l2_cache_sync() {
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let regs = RegisterBlock::new();
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regs.reg7_cache_sync.write(Reg7CacheSync::zeroed().c(false));
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}
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#[inline(always)]
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pub fn l2_cache_clean(addr: usize) {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_clean_pa.write(addr as u32);
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}
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}
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#[inline(always)]
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pub fn l2_cache_invalidate(addr: usize) {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_inv_pa.write(addr as u32);
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}
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}
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#[inline(always)]
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pub fn l2_cache_clean_invalidate(addr: usize) {
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let regs = RegisterBlock::new();
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unsafe {
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regs.reg7_clean_inv_pa.write(addr as u32);
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}
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}
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#[repr(C)]
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struct RegisterBlock {
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/// cache ID register, Returns the 32-bit device ID code it reads off the CACHEID input bus.
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/// The value is specified by the system integrator. Reset value: 0x410000c8
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pub reg0_cache_id: Reg0CacheId,
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/// cache type register, Returns the 32-bit cache type. Reset value: 0x1c100100
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pub reg0_cache_type: Reg0CacheType,
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unused0: [u32; 62],
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/// control register, reset value: 0x0
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pub reg1_control: Reg1Control,
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/// auxilary control register, reset value: 0x02020000
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pub reg1_aux_control: Reg1AuxControl,
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/// Configures Tag RAM latencies
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pub reg1_tag_ram_control: Reg1TagRamControl,
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/// configures data RAM latencies
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pub reg1_data_ram_control: Reg1DataRamControl,
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unused1: [u32; 60],
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/// Permits the event counters to be enabled and reset.
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pub reg2_ev_counter_ctrl: Reg2EvCounterCtrl,
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/// Enables event counter 1 to be driven by a specific event. Counter 1 increments when the
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/// event occurs.
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pub reg2_ev_counter1_cfg: Reg2EvCounter1Cfg,
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/// Enables event counter 0 to be driven by a specific event. Counter 0 increments when the
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/// event occurs.
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pub reg2_ev_counter0_cfg: Reg2EvCounter0Cfg,
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/// Enable the programmer to read off the counter value. The counter counts an event as
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/// specified by the Counter Configuration Registers. The counter can be preloaded if counting
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/// is disabled and reset by the Event Counter Control Register.
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pub reg2_ev_counter1: RW<u32>,
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/// Enable the programmer to read off the counter value. The counter counts an event as
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/// specified by the Counter Configuration Registers. The counter can be preloaded if counting
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/// is disabled and reset by the Event Counter Control Register.
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pub reg2_ev_counter0: RW<u32>,
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/// This register enables or masks interrupts from being triggered on the external pins of the
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/// cache controller. Figure 3-8 on page 3-17 shows the register bit assignments. The bit
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/// assignments enables the masking of the interrupts on both their individual outputs and the
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/// combined L2CCINTR line. Clearing a bit by writing a 0, disables the interrupt triggering on
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/// that pin. All bits are cleared by a reset. You must write to the register bits with a 1 to
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/// enable the generation of interrupts. 1 = Enabled. 0 = Masked. This is the default.
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pub reg2_int_mask: Reg2IntMask,
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/// This register is a read-only.It returns the masked interrupt status. This register can be
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/// accessed by secure and non-secure operations. The register gives an AND function of the raw
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/// interrupt status with the values of the interrupt mask register. All the bits are cleared
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/// by a reset. A write to this register is ignored. Bits read can be HIGH or LOW: HIGH If the
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/// bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW If
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/// the bits read LOW, either no interrupt has been generated, or the interrupt is masked.
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pub reg2_int_mask_status: Reg2IntMaskStatus,
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/// The Raw Interrupt Status Register enables the interrupt status that excludes the masking
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/// logic. Bits read can be HIGH or LOW: HIGH If the bits read HIGH, they reflect the status of
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/// the input lines triggering an interrupt. LOW If the bits read LOW, no interrupt has been
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/// generated.
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pub reg2_int_raw_status: Reg2IntRawStatus,
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/// Clears the Raw Interrupt Status Register bits. When a bit is written as 1, it clears the
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/// corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has
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/// no effect
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pub reg2_int_clear: Reg2IntClear,
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unused2: [u32; 323],
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/// Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and EB, are empty
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pub reg7_cache_sync: Reg7CacheSync,
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unused3: [u32; 15],
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/// Invalidate Line by PA: Specific L2 cache line is marked as not valid
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pub reg7_inv_pa: RW<u32>,
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unused4: [u32; 2],
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/// Invalidate by Way Invalidate all data in specified ways, including dirty data. An
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/// Invalidate by way while selecting all cache ways is equivalent to invalidating all cache
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/// entries. Completes as a background task with the way, or ways, locked, preventing
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/// allocation.
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pub reg7_inv_way: RW<u32>,
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unused5: [u32; 12],
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/// Clean Line by PA Write the specific L2 cache line to L3 main memory if the line is marked
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/// as valid and dirty. The line is marked as not dirty. The valid bit is unchanged
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pub reg7_clean_pa: RW<u32>,
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unused6: [u32; 1],
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/// Clean Line by Set/Way Write the specific L2 cache line within the specified way to L3 main
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/// memory if the line is marked as valid and dirty. The line is marked as not dirty. The valid
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/// bit is unchanged
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pub reg7_clean_index: Reg7CleanIndex,
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/// Clean by Way Writes each line of the specified L2 cache ways to L3 main memory if the line
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/// is marked as valid and dirty. The lines are marked as not dirty. The valid bits are
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/// unchanged. Completes as a background task with the way, or ways, locked, preventing
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/// allocation.
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pub reg7_clean_way: RW<u32>,
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unused7: [u32; 12],
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/// Clean and Invalidate Line by PA Write the specific L2 cache line to L3 main memory if the
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/// line is marked as valid and dirty. The line is marked as not valid
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pub reg7_clean_inv_pa: RW<u32>,
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unused8: [u32; 1],
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/// Clean and Invalidate Line by Set/Way Write the specific L2 cache line within the specified
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/// way to L3 main memory if the line is marked as valid and dirty. The line is marked as not
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/// valid
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pub reg7_clean_inv_index: Reg7CleanInvIndex,
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/// Clean and Invalidate by Way Writes each line of the specified L2 cache ways to L3 main
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/// memory if the line is marked as valid and dirty. The lines are marked as not valid.
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/// Completes as a background task with the way, or ways, locked, preventing allocation.
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pub reg7_clean_inv_way: RW<u32>,
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unused9: [u32; 0x1D8],
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pub reg15_prefetch_ctrl: Reg15PrefetechCtrl,
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}
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register_at!(RegisterBlock, 0xF8F02000, new);
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register!(reg0_cache_id, Reg0CacheId, RW, u32);
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register_bits!(reg0_cache_id, implementer, u8, 24, 31);
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register_bits!(reg0_cache_id, cache_id, u8, 10, 15);
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register_bits!(reg0_cache_id, part_num, u8, 6, 9);
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register_bits!(reg0_cache_id, rtl_release, u8, 0, 5);
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register!(reg0_cache_type, Reg0CacheType, RW, u32);
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register_bit!(reg0_cache_type, data_banking, 31);
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register_bits!(reg0_cache_type, ctype, u8, 25, 28);
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register_bit!(reg0_cache_type, h, 24);
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register_bits!(reg0_cache_type, dsize_middsize_19, u8, 20, 22);
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register_bit!(reg0_cache_type, l2_assoc_d, 18);
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register_bits!(reg0_cache_type, l2cache_line_len_disize_11, u8, 12, 13);
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register_bits!(reg0_cache_type, isize_midisize_7, u8, 8, 10);
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register_bit!(reg0_cache_type, l2_assoc_i, 6);
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register_bits!(reg0_cache_type, l2cache_line_len_i, u8, 0, 1);
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register!(reg1_control, Reg1Control, RW, u32);
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register_bit!(reg1_control, l2_enable, 0);
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register!(reg1_aux_control, Reg1AuxControl, RW, u32);
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register_bit!(reg1_aux_control, early_bresp_en, 30);
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register_bit!(reg1_aux_control, instr_prefetch_en, 29);
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register_bit!(reg1_aux_control, data_prefetch_en, 28);
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register_bit!(reg1_aux_control, nonsec_inte_access_ctrl, 27);
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register_bit!(reg1_aux_control, nonsec_lockdown_en, 26);
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register_bit!(reg1_aux_control, cache_replace_policy, 25);
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register_bits!(reg1_aux_control, force_write_alloc, u8, 23, 24);
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register_bit!(reg1_aux_control, shared_attr_override_en, 22);
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register_bit!(reg1_aux_control, parity_en, 21);
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register_bit!(reg1_aux_control, event_mon_bus_en, 20);
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register_bits!(reg1_aux_control, way_size, u8, 17, 19);
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register_bit!(reg1_aux_control, associativity, 16);
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register_bit!(reg1_aux_control, shared_attr_inva_en, 13);
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register_bit!(reg1_aux_control, ex_cache_config, 12);
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register_bit!(reg1_aux_control, store_buff_dev_lim_en, 11);
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register_bit!(reg1_aux_control, high_pr_so_dev_rd_en, 10);
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register_bit!(reg1_aux_control, full_line_zero_enable, 0);
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register!(reg1_tag_ram_control, Reg1TagRamControl, RW, u32);
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register_bits!(reg1_tag_ram_control, ram_wr_access_lat, u8, 8, 10);
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register_bits!(reg1_tag_ram_control, ram_rd_access_lat, u8, 4, 6);
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register_bits!(reg1_tag_ram_control, ram_setup_lat, u8, 0, 2);
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register!(reg1_data_ram_control, Reg1DataRamControl, RW, u32);
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register_bits!(reg1_data_ram_control, ram_wr_access_lat, u8, 8, 10);
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register_bits!(reg1_data_ram_control, ram_rd_access_lat, u8, 4, 6);
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register_bits!(reg1_data_ram_control, ram_setup_lat, u8, 0, 2);
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register!(reg2_ev_counter_ctrl, Reg2EvCounterCtrl, RW, u32);
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register_bit!(reg2_ev_counter_ctrl, ev_ctr_en, 0);
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register!(reg2_ev_counter1_cfg, Reg2EvCounter1Cfg, RW, u32);
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register_bits!(reg2_ev_counter1_cfg, ctr_ev_src, u8, 2, 5);
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register_bits!(reg2_ev_counter1_cfg, ev_ctr_intr_gen, u8, 0, 1);
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register!(reg2_ev_counter0_cfg, Reg2EvCounter0Cfg, RW, u32);
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register_bits!(reg2_ev_counter0_cfg, ctr_ev_src, u8, 2, 5);
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register_bits!(reg2_ev_counter0_cfg, ev_ctr_intr_gen, u8, 0, 1);
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register!(reg2_int_mask, Reg2IntMask, RW, u32);
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register_bit!(reg2_int_mask, decerr, 8);
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register_bit!(reg2_int_mask, slverr, 7);
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register_bit!(reg2_int_mask, errrd, 6);
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register_bit!(reg2_int_mask, errrt, 5);
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register_bit!(reg2_int_mask, errwd, 4);
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register_bit!(reg2_int_mask, errwt, 3);
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register_bit!(reg2_int_mask, parrd, 2);
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register_bit!(reg2_int_mask, parrt, 1);
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register_bit!(reg2_int_mask, ecntr, 0);
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register!(reg2_int_mask_status, Reg2IntMaskStatus, RW, u32);
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register_bit!(reg2_int_mask_status, decerr, 8);
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register_bit!(reg2_int_mask_status, slverr, 7);
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register_bit!(reg2_int_mask_status, errrd, 6);
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register_bit!(reg2_int_mask_status, errrt, 5);
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register_bit!(reg2_int_mask_status, errwd, 4);
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register_bit!(reg2_int_mask_status, errwt, 3);
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register_bit!(reg2_int_mask_status, parrd, 2);
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register_bit!(reg2_int_mask_status, parrt, 1);
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register_bit!(reg2_int_mask_status, ecntr, 0);
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register!(reg2_int_raw_status, Reg2IntRawStatus, RW, u32);
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register_bit!(reg2_int_raw_status, decerr, 8);
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register_bit!(reg2_int_raw_status, slverr, 7);
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register_bit!(reg2_int_raw_status, errrd, 6);
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register_bit!(reg2_int_raw_status, errrt, 5);
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register_bit!(reg2_int_raw_status, errwd, 4);
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register_bit!(reg2_int_raw_status, errwt, 3);
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register_bit!(reg2_int_raw_status, parrd, 2);
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register_bit!(reg2_int_raw_status, parrt, 1);
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register_bit!(reg2_int_raw_status, ecntr, 0);
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register!(reg2_int_clear, Reg2IntClear, RW, u32, 0);
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register_bit!(reg2_int_clear, decerr, 8, WTC);
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register_bit!(reg2_int_clear, slverr, 7, WTC);
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register_bit!(reg2_int_clear, errrd, 6, WTC);
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register_bit!(reg2_int_clear, errrt, 5, WTC);
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register_bit!(reg2_int_clear, errwd, 4, WTC);
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register_bit!(reg2_int_clear, errwt, 3, WTC);
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register_bit!(reg2_int_clear, parrd, 2, WTC);
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register_bit!(reg2_int_clear, parrt, 1, WTC);
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register_bit!(reg2_int_clear, ecntr, 0, WTC);
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register!(reg7_cache_sync, Reg7CacheSync, RW, u32);
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register_bit!(reg7_cache_sync, c, 0);
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register!(reg7_clean_index, Reg7CleanIndex, RW, u32);
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register_bits!(reg7_clean_index, way, u8, 28, 30);
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register_bits!(reg7_clean_index, index, u8, 5, 11);
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register_bit!(reg7_clean_index, c, 0);
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register!(reg7_clean_inv_index, Reg7CleanInvIndex, RW, u32);
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register_bits!(reg7_clean_inv_index, way, u8, 28, 30);
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register_bits!(reg7_clean_inv_index, index, u8, 5, 11);
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register_bit!(reg7_clean_inv_index, c, 0);
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register!(reg15_prefetch_ctrl, Reg15PrefetechCtrl, RW, u32);
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register_bit!(reg15_prefetch_ctrl, double_linefill_en, 30);
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register_bit!(reg15_prefetch_ctrl, instr_prefetch_en, 29);
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register_bit!(reg15_prefetch_ctrl, data_prefetch_en, 28);
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register_bit!(reg15_prefetch_ctrl, pref_drop_en, 24);
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register_bit!(reg15_prefetch_ctrl, incr_double_linefill_en, 23);
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register_bits!(reg15_prefetch_ctrl, prefetch_offset, u8, 0, 4);
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