122 lines
3.2 KiB
Rust
122 lines
3.2 KiB
Rust
use libregister::{RegisterR, RegisterRW};
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use super::slcr;
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pub use slcr::ArmPllSource;
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pub mod source;
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use source::*;
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enum CpuClockMode {
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/// Clocks run in 4:2:2:1 mode
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C421,
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/// Clocks run in 6:3:2:1 mode
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C621,
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}
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impl CpuClockMode {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::slcr();
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if regs.clk_621_true.read().clk_621_true() {
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CpuClockMode::C621
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} else {
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CpuClockMode::C421
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}
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}
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}
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#[derive(Debug, Clone)]
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pub struct Clocks {
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/// ARM PLL: Recommended clock source for the CPUs and the interconnect
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pub arm: u32,
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/// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
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pub ddr: u32,
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/// I/O PLL: Recommended clock for I/O peripherals
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pub io: u32,
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}
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impl Clocks {
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pub fn get() -> Self {
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Clocks {
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arm: ArmPll::freq(),
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ddr: DdrPll::freq(),
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io: IoPll::freq(),
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}
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}
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pub fn set_cpu_freq(target_freq: u32) {
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let arm_pll = ArmPll::freq();
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// 1 and 3 cannot be used
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let mut div = 2u8;
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while div == 3 || (div < 63 && arm_pll / u32::from(div) > target_freq) {
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div += 1;
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}
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.arm_clk_ctrl.modify(|_, w| w
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.srcsel(ArmPllSource::ArmPll)
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.divisor(div)
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);
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})
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}
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pub fn cpu_6x4x(&self) -> u32 {
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let slcr = slcr::RegisterBlock::slcr();
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let arm_clk_ctrl = slcr.arm_clk_ctrl.read();
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let pll = match arm_clk_ctrl.srcsel() {
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ArmPllSource::ArmPll => self.arm,
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ArmPllSource::DdrPll => self.ddr,
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ArmPllSource::IoPll => self.io,
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};
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pll / u32::from(arm_clk_ctrl.divisor())
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}
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pub fn cpu_3x2x(&self) -> u32 {
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self.cpu_6x4x() / 2
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}
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pub fn cpu_2x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 2,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 3,
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}
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}
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pub fn cpu_1x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 4,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 6,
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}
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}
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pub fn uart_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::slcr();
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let uart_clk_ctrl = regs.uart_clk_ctrl.read();
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let pll = match uart_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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self.arm,
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slcr::PllSource::DdrPll =>
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self.ddr,
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slcr::PllSource::IoPll =>
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self.io,
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};
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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pub fn sdio_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::slcr();
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let sdio_clk_ctrl = regs.sdio_clk_ctrl.read();
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let pll = match sdio_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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self.arm,
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slcr::PllSource::DdrPll =>
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self.ddr,
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slcr::PllSource::IoPll =>
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self.io,
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};
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pll / u32::from(sdio_clk_ctrl.divisor())
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}
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}
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