libcortex_a9: added interrupt_handler macro #77
@ -34,6 +34,20 @@ SECTIONS
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__bss_end = .;
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__bss_end = .;
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} > OCM3
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} > OCM3
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.irq_stack1 (NOLOAD) : ALIGN(8)
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{
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__irq_stack1_end = .;
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. += 0x100;
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__irq_stack1_start = .;
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} > OCM3
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.irq_stack0 (NOLOAD) : ALIGN(8)
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{
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__irq_stack0_end = .;
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. += 0x100;
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__irq_stack0_start = .;
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} > OCM3
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.stack1 (NOLOAD) : ALIGN(8) {
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.stack1 (NOLOAD) : ALIGN(8) {
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__stack1_end = .;
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__stack1_end = .;
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. += 0x200;
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. += 0x200;
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@ -55,7 +55,7 @@ extern "C" {
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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interrupt_handler!(IRQ, irq, __stack0_start, __stack1_start, {
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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if MPIDR.read().cpu_id() == 1{
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let mut gic = gic::InterruptController::gic(mpcore);
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@ -2,25 +2,25 @@ use libregister::RegisterR;
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use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler};
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use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler};
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use libboard_zynq::{println, stdio};
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use libboard_zynq::{println, stdio};
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interrupt_handler!(UndefinedInstruction, undefined_instruction, __stack0_start, __stack1_start, {
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interrupt_handler!(UndefinedInstruction, undefined_instruction, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("UndefinedInstruction");
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println!("UndefinedInstruction");
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loop {}
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loop {}
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});
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});
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interrupt_handler!(SoftwareInterrupt, software_interrupt, __stack0_start, __stack1_start, {
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interrupt_handler!(SoftwareInterrupt, software_interrupt, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("SoftwareInterrupt");
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println!("SoftwareInterrupt");
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loop {}
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loop {}
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});
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});
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interrupt_handler!(PrefetchAbort, prefetch_abort, __stack0_start, __stack1_start, {
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interrupt_handler!(PrefetchAbort, prefetch_abort, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("PrefetchAbort");
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println!("PrefetchAbort");
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loop {}
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loop {}
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});
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});
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interrupt_handler!(DataAbort, data_abort, __stack0_start, __stack1_start, {
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interrupt_handler!(DataAbort, data_abort, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("DataAbort on core {}", MPIDR.read().cpu_id());
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println!("DataAbort on core {}", MPIDR.read().cpu_id());
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@ -29,20 +29,20 @@ interrupt_handler!(DataAbort, data_abort, __stack0_start, __stack1_start, {
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loop {}
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loop {}
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});
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});
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interrupt_handler!(ReservedException, reserved_exception, __stack0_start, __stack1_start, {
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interrupt_handler!(ReservedException, reserved_exception, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("ReservedException");
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println!("ReservedException");
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loop {}
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loop {}
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});
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});
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#[cfg(feature = "dummy_irq_handler")]
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#[cfg(feature = "dummy_irq_handler")]
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interrupt_handler!(IRQ, irq, __stack0_start, __stack1_start, {
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("IRQ");
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println!("IRQ");
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loop {}
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loop {}
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});
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});
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interrupt_handler!(FIQ, fiq, __stack0_start, __stack1_start, {
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interrupt_handler!(FIQ, fiq, __irq_stack0_start, __irq_stack1_start, {
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stdio::drop_uart();
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stdio::drop_uart();
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println!("FIQ");
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println!("FIQ");
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loop {}
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loop {}
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@ -2,7 +2,7 @@ use r0::zero_bss;
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use core::ptr::write_volatile;
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use core::ptr::write_volatile;
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use libregister::{
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use libregister::{
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VolatileCell,
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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RegisterR, RegisterRW,
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};
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};
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use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu, interrupt_handler};
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use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu, interrupt_handler};
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use libboard_zynq::{slcr, mpcore};
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use libboard_zynq::{slcr, mpcore};
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@ -19,16 +19,15 @@ extern "C" {
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static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
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static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
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interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, {
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interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, {
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// no need to setup stack here, as we already did when entering the handler
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match MPIDR.read().cpu_id() {
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match MPIDR.read().cpu_id() {
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0 => {
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0 => {
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SP.write(&mut __stack0_start as *mut _ as u32);
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boot_core0();
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boot_core0();
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}
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}
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1 => {
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1 => {
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while !CORE1_ENABLED.get() {
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while !CORE1_ENABLED.get() {
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spin_lock_yield();
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spin_lock_yield();
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}
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}
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SP.write(&mut __stack1_start as *mut _ as u32);
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boot_core1();
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boot_core1();
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}
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}
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_ => unreachable!(),
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_ => unreachable!(),
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15
szl/link.x
15
szl/link.x
@ -59,6 +59,21 @@ SECTIONS
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__stack0_start = .;
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__stack0_start = .;
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} > OCM3
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} > OCM3
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.irq_stack1 (NOLOAD) : ALIGN(8)
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{
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__irq_stack1_end = .;
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. += 0x100;
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__irq_stack1_start = .;
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} > OCM3
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.irq_stack0 (NOLOAD) : ALIGN(8)
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{
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__irq_stack0_end = .;
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. += 0x100;
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__irq_stack0_start = .;
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} > OCM3
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/DISCARD/ :
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/DISCARD/ :
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{
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{
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/* Unused exception related info that only wastes space */
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/* Unused exception related info that only wastes space */
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