sdio-registers #29
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@ -17,4 +17,5 @@ pub mod flash;
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pub mod dmac;
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pub mod dmac;
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pub mod time;
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pub mod time;
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pub mod timer;
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pub mod timer;
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pub mod sdio;
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pub mod logger;
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pub mod logger;
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@ -0,0 +1 @@
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mod regs;
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@ -0,0 +1,547 @@
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use volatile_register::{RO, RW, WO};
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use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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pub sdma_system_address: RW<u32>,
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pub block_size_block_count: BlockSizeBlockCount,
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pub argument: RW<u32>,
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pub transfer_mode_command: TransferModeCommand,
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pub responses: [RO<u32>; 4],
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pub buffer: RW<u32>,
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pub present_state: PresentState,
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/// Host. power, block gap, wakeup control
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pub control: Control,
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/// Clock and timeout control, and software reset register.
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pub timing_control: TimingControl,
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pub interrupt_status: InterruptStatus,
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pub interrupt_status_en: InterruptStatusEn,
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pub interrupt_signal_en: InterruptSignalEn,
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pub auto_cmd12_error_status: AutoCmd12ErrorStatus,
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pub capabilities: Capabilities,
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pub max_current_capabilities: MaxCurrentCapabilities,
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pub force_event: ForceEvent,
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pub adma_error_status: AdmaErrorStatus,
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pub adma_system_address: RW<u32>,
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pub boot_data_timeout_counter: RW<u32>,
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pub debug_selection: DebugSelection,
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pub spi_interrupt_support: SpiInterruptSupport,
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pub misc_reg: MiscReg,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum CommandType {
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Normal = 0b00,
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Suspend = 0b01,
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Resume = 0b10,
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Abort = 0b11,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum ResponseTypeSelect {
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NoResponse = 0b00,
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Length136 = 0b01,
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Length48 = 0b10,
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Legnth48Check = 0b11,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum BusVoltage {
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/// 3.3V
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V33 = 0b111,
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/// 3.0V, typ.
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V30 = 0b110,
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/// 1.8V, typ.
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V18 = 0b101,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum DmaSelect {
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SDMA = 0b00,
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ADMA1 = 0b01,
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ADMA2 = 0b10,
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ADMA3 = 0b11,
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}
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#[allow(unused)]
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#[repr(u8)]
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/// SDCLK Frequency divisor, d(number) means baseclock divided by (number).
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pub enum SdclkFreqDivisor {
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D256 = 0x80,
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D128 = 0x40,
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D64 = 0x20,
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D32 = 0x10,
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D16 = 0x08,
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D8 = 0x04,
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D4 = 0x02,
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D2 = 0x01,
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D1 = 0x00,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum AdmaErrorState {
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StStop = 0b00,
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StFds = 0b01,
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StTfr = 0b11,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum SpecificationVersion {
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V1 = 0,
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V2 = 1,
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}
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register_at!(RegisterBlock, 0xE0100000, sd0);
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register_at!(RegisterBlock, 0xE0101000, sd1);
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register!(block_size_block_count, BlockSizeBlockCount, RW, u32);
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register_bits!(
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block_size_block_count,
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/// Current transfer block count.
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blocks_count,
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u16,
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16,
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31
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);
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register_bits!(
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block_size_block_count,
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/// Host SDMA Buffer Size, size = 2^(val + 2) KB.
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dma_buffer_size,
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u8,
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12,
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14
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);
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register_bits!(
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block_size_block_count,
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/// Block size for data transfer. Unit: byte.
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transfer_block_size,
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u16,
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0,
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11
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);
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register!(transfer_mode_command, TransferModeCommand, RW, u32);
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register_bits!(
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transfer_mode_command,
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/// Command Number.
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command_index,
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u8,
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24,
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29
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);
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register_bits_typed!(
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transfer_mode_command,
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/// Command type register.
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command_type,
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u8,
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CommandType,
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22,
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23
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);
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register_bit!(
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transfer_mode_command,
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/// 1 if data is present and shall be transferred using the DAT line.
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data_present_select,
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21
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);
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register_bit!(
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transfer_mode_command,
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/// If the index field shall be checked.
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index_check_en,
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20
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);
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register_bit!(
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transfer_mode_command,
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/// If CRC shall be checked.
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crc_check_en,
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19
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);
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register_bits_typed!(
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transfer_mode_command,
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/// Different type of response.
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response_type_select,
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u8,
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ResponseTypeSelect,
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16,
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17
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);
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register_bit!(
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transfer_mode_command,
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/// Enables the multi block DAT line data transfer.
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multi_block_en,
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5
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);
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register_bit!(
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transfer_mode_command,
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/// 1 if read (card to host), 0 if write (host to card).
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direction_select,
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4
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);
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register_bit!(
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transfer_mode_command,
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/// If CMD12 shall be issued automatically when last block transfer is completed.
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auto_cmd12_en,
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2
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);
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register_bit!(
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transfer_mode_command,
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/// Enable the block count register.
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block_count_en,
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1
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);
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register_bit!(
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transfer_mode_command,
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/// Enable DMA,
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dma_en,
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0
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);
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register!(present_state, PresentState, RO, u32);
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register_bit!(
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present_state,
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/// CMD Line Signal Level.
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cmd_line_level,
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24
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);
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register_bit!(
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present_state,
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/// Signal level in DAT[3]
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dat3_level,
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23
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);
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register_bit!(
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present_state,
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/// Signal level in DAT[2]
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dat2_level,
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22
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);
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register_bit!(
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present_state,
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/// Signal level in DAT[1]
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dat1_level,
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21
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);
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register_bit!(
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present_state,
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/// Signal level in DAT[0]
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dat0_level,
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20
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);
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register_bit!(
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present_state,
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/// Write enabled and inverse of SDx_WP pin level.
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write_enabled,
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19
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);
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register_bit!(
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present_state,
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/// Card detected and inverse of SDx_CDn pin level.
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card_detected,
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18
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);
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register_bit!(present_state, card_state_stable, 17);
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register_bit!(present_state, card_inserted, 16);
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register_bit!(present_state, buffer_read_en, 11);
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register_bit!(present_state, buffer_write_en, 10);
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register_bit!(present_state, read_transfer_active, 9);
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register_bit!(present_state, write_transfer_active, 8);
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register_bit!(present_state, dat_line_active, 2);
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register_bit!(present_state, command_inhibit_dat, 1);
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register_bit!(present_state, command_inhibit_cmd, 0);
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register!(control, Control, RW, u32);
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register_bit!(
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control,
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/// Enable wakeup event via SD card removal assertion.
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wakeup_on_removal,
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26
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);
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register_bit!(
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control,
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/// Enable wakeup event via SD card insertion assertion.
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wakeup_on_insertion,
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25
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);
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register_bit!(
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control,
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/// Enable wakeup event via card interrupt assertion.
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wakeup_on_interrupt,
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24
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);
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register_bit!(
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control,
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///Enable interrupt detection at the block gap for a multiple block transfer.
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interrupt_at_block_gap,
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19
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);
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register_bit!(
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control,
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/// Enable the use of the read wait protocol.
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read_wait_control,
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18
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);
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register_bit!(
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control,
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/// Restart a trasaction which was stopped using the stop at block gap request.
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continue_req,
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17
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);
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register_bit!(
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control,
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/// Stop executing a transaction at the next block gap.
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stop_at_block_gap_req,
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16
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);
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register_bits_typed!(control, bus_voltage, u8, BusVoltage, 9, 11);
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register_bit!(control, bus_power, 8);
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register_bit!(
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control,
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/// Selects source for card detection. 0 for SDCD#, 1 for card detect test level.
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card_detect_signal,
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7
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);
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register_bit!(
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control,
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/// Indicates card inserted or not. Enabled when card detect signal is 1.
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card_detect_test_level,
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6
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);
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register_bits_typed!(control, dma_select, u8, DmaSelect, 3, 4);
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register_bit!(control, high_speed_en, 2);
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register_bit!(
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control,
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/// Select the data width of the HC. 1 for 4-bit, 0 for 1-bit.
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data_width_select,
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1
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);
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register_bit!(
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control,
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/// 1 for LED on, 0 for LED off.
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led_control,
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0
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);
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register!(timing_control, TimingControl, RW, u32);
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register_bit!(
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timing_control,
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/// Software reset for DAT line.
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software_reset_dat,
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26
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);
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register_bit!(
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timing_control,
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/// Software reset for CMD line.
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software_reset_cmd,
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|
25
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);
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register_bit!(
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timing_control,
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/// Software reset for ALL.
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software_reset_all,
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24
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);
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register_bits!(
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timing_control,
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/// Determines the interval by which DAT line time-outs are detected.
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/// Interval = TMCLK * 2^(13 + val)
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/// Note: 0b1111 is reserved.
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timeout_counter_value,
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u8,
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16,
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|
19
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|
);
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register_bits_typed!(
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timing_control,
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/// Selects the frequency divisor, thus the clock frequency for SDCLK.
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/// Choose the smallest possible divisor which results in a clock frequency
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/// that is less than or equal to the target frequency.
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|
sdclk_freq_divisor,
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|
u8,
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SdclkFreqDivisor,
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|
8,
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|
15
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|
);
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register_bit!(timing_control, sd_clk_en, 2);
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|
register_bit!(
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|
timing_control,
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/// 1 when SD clock is stable.
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/// Note that this field is read-only.
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|
internal_clk_stable,
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|
1,
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|
RO
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);
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|
register_bit!(timing_control, internal_clk_en, 0);
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|
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register!(interrupt_status, InterruptStatus, RW, u32, 1 << 15 | 1 << 8);
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register_bit!(interrupt_status, ceata_error, 29, WTC);
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register_bit!(interrupt_status, target_response_error, 28, WTC);
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register_bit!(interrupt_status, adma_error, 25, WTC);
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register_bit!(interrupt_status, auto_cmd12_error, 24, WTC);
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register_bit!(interrupt_status, current_limit_error, 23, WTC);
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register_bit!(interrupt_status, data_end_bit_error, 22, WTC);
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register_bit!(interrupt_status, data_crc_error, 21, WTC);
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register_bit!(interrupt_status, data_timeout_error, 20, WTC);
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register_bit!(interrupt_status, command_index_error, 19, WTC);
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register_bit!(interrupt_status, command_end_bit_error, 18, WTC);
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register_bit!(interrupt_status, command_crc_error, 17, WTC);
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register_bit!(interrupt_status, command_timeout_error, 16, WTC);
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register_bit!(interrupt_status, error_interrupt, 15, RO);
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register_bit!(interrupt_status, boot_terminate_interrupt, 10, WTC);
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register_bit!(interrupt_status, boot_ack_rcv, 9, WTC);
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register_bit!(interrupt_status, card_interrupt, 8, RO);
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register_bit!(interrupt_status, card_removal, 7, WTC);
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register_bit!(interrupt_status, card_insertion, 6, WTC);
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register_bit!(interrupt_status, buffer_read_ready, 5, WTC);
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register_bit!(interrupt_status, buffer_write_ready, 4, WTC);
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register_bit!(interrupt_status, dma_interrupt, 3, WTC);
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register_bit!(interrupt_status, block_gap_event, 2, WTC);
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|
register_bit!(interrupt_status, transfer_complete, 1, WTC);
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|
register_bit!(interrupt_status, command_complete, 0, WTC);
|
||||||
|
|
||||||
|
register!(interrupt_status_en, InterruptStatusEn, RW, u32);
|
||||||
|
register_bit!(interrupt_status_en, ceata_error_status_en, 29);
|
||||||
|
register_bit!(interrupt_status_en, target_response_error_status_en, 28);
|
||||||
|
register_bit!(interrupt_status_en, adma_error_status_en, 25);
|
||||||
|
register_bit!(interrupt_status_en, auto_cmd12_error_status_en, 24);
|
||||||
|
register_bit!(interrupt_status_en, current_limit_error_status_en, 23);
|
||||||
|
register_bit!(interrupt_status_en, data_end_bit_error_status_en, 22);
|
||||||
|
register_bit!(interrupt_status_en, data_crc_error_status_en, 21);
|
||||||
|
register_bit!(interrupt_status_en, data_timeout_error_status_en, 20);
|
||||||
|
register_bit!(interrupt_status_en, cmd_index_error_status_en, 19);
|
||||||
|
register_bit!(interrupt_status_en, cmd_end_bit_error_status_en, 18);
|
||||||
|
register_bit!(interrupt_status_en, cmd_crc_error_status_en, 17);
|
||||||
|
register_bit!(interrupt_status_en, cmd_timeout_error_status_en, 16);
|
||||||
|
register_bit!(interrupt_status_en, fixed_to_0, 15, RO);
|
||||||
|
register_bit!(interrupt_status_en, boot_terminate_interrupt_en, 10);
|
||||||
|
register_bit!(interrupt_status_en, boot_ack_rcv_en, 9);
|
||||||
|
register_bit!(interrupt_status_en, card_interrupt_status_en, 8);
|
||||||
|
register_bit!(interrupt_status_en, card_removal_status_en, 7);
|
||||||
|
register_bit!(interrupt_status_en, card_insertion_status_en, 6);
|
||||||
|
register_bit!(interrupt_status_en, buffer_read_ready_status_en, 5);
|
||||||
|
register_bit!(interrupt_status_en, buffer_write_ready_status_en, 4);
|
||||||
|
register_bit!(interrupt_status_en, dma_interrupt_status_en, 3);
|
||||||
|
register_bit!(interrupt_status_en, block_gap_evt_status_en, 2);
|
||||||
|
register_bit!(interrupt_status_en, transfer_complete_status_en, 1);
|
||||||
|
register_bit!(interrupt_status_en, cmd_complete_status_en, 0);
|
||||||
|
|
||||||
|
register!(interrupt_signal_en, InterruptSignalEn, RW, u32);
|
||||||
|
register_bit!(interrupt_signal_en, ceata_error_signal_en, 29);
|
||||||
|
register_bit!(interrupt_signal_en, target_response_error_signal_en, 28);
|
||||||
|
register_bit!(interrupt_signal_en, adma_error_signal_en, 25);
|
||||||
|
register_bit!(interrupt_signal_en, auto_cmd12_error_signal_en, 24);
|
||||||
|
register_bit!(interrupt_signal_en, current_limit_error_signal_en, 23);
|
||||||
|
register_bit!(interrupt_signal_en, data_end_bit_error_signal_en, 22);
|
||||||
|
register_bit!(interrupt_signal_en, data_crc_error_signal_en, 21);
|
||||||
|
register_bit!(interrupt_signal_en, data_timeout_error_signal_en, 20);
|
||||||
|
register_bit!(interrupt_signal_en, cmd_index_error_signal_en, 19);
|
||||||
|
register_bit!(interrupt_signal_en, cmd_end_bit_error_signal_en, 18);
|
||||||
|
register_bit!(interrupt_signal_en, cmd_crc_error_signal_en, 17);
|
||||||
|
register_bit!(interrupt_signal_en, cmd_timeout_error_signal_en, 16);
|
||||||
|
register_bit!(interrupt_signal_en, fixed_to_0, 15, RO);
|
||||||
|
register_bit!(interrupt_signal_en, boot_terminate_interrupt_signal_en, 10);
|
||||||
|
register_bit!(interrupt_signal_en, boot_ack_rcv_signal_en, 9);
|
||||||
|
register_bit!(interrupt_signal_en, card_interrupt_signal_en, 8);
|
||||||
|
register_bit!(interrupt_signal_en, card_removal_signal_en, 7);
|
||||||
|
register_bit!(interrupt_signal_en, card_insertion_signal_en, 6);
|
||||||
|
register_bit!(interrupt_signal_en, buffer_read_ready_signal_en, 5);
|
||||||
|
register_bit!(interrupt_signal_en, buffer_write_ready_signal_en, 4);
|
||||||
|
register_bit!(interrupt_signal_en, dma_interrupt_signal_en, 3);
|
||||||
|
register_bit!(interrupt_signal_en, block_gap_evt_signal_en, 2);
|
||||||
|
register_bit!(interrupt_signal_en, transfer_complete_signal_en, 1);
|
||||||
|
register_bit!(interrupt_signal_en, cmd_complete_signal_en, 0);
|
||||||
|
|
||||||
|
register!(auto_cmd12_error_status, AutoCmd12ErrorStatus, RO, u32);
|
||||||
|
register_bit!(
|
||||||
|
auto_cmd12_error_status,
|
||||||
|
cmd_not_issued_by_auto_cmd12_error,
|
||||||
|
7
|
||||||
|
);
|
||||||
|
register_bit!(auto_cmd12_error_status, index_error, 4);
|
||||||
|
register_bit!(auto_cmd12_error_status, end_bit_error, 3);
|
||||||
|
register_bit!(auto_cmd12_error_status, crc_error, 2);
|
||||||
|
register_bit!(auto_cmd12_error_status, timeout_error, 1);
|
||||||
|
register_bit!(auto_cmd12_error_status, not_executed, 0);
|
||||||
|
|
||||||
|
register!(capabilities, Capabilities, RO, u32);
|
||||||
|
register_bit!(capabilities, spi_block_mode, 30);
|
||||||
|
register_bit!(capabilities, spi_mode, 29);
|
||||||
|
register_bit!(capabilities, support_64bit, 28);
|
||||||
|
register_bit!(capabilities, interrupt_mode, 27);
|
||||||
|
register_bit!(capabilities, voltage_1_8, 26);
|
||||||
|
register_bit!(capabilities, voltage_3_0, 25);
|
||||||
|
register_bit!(capabilities, voltage_3_3, 24);
|
||||||
|
register_bit!(capabilities, suspend_resume, 23);
|
||||||
|
register_bit!(capabilities, sdma, 22);
|
||||||
|
register_bit!(capabilities, hgih_speed, 21);
|
||||||
|
register_bit!(capabilities, adma2, 19);
|
||||||
|
register_bit!(capabilities, extended_media_bus, 18);
|
||||||
|
register_bits!(
|
||||||
|
capabilities,
|
||||||
|
/// Length = 2^(9 + v) bytes.
|
||||||
|
max_block_len,
|
||||||
|
u8,
|
||||||
|
16,
|
||||||
|
17
|
||||||
|
);
|
||||||
|
register_bit!(capabilities, timeout_clock_unit, 7);
|
||||||
|
|
||||||
|
register!(max_current_capabilities, MaxCurrentCapabilities, RO, u32);
|
||||||
|
register_bits!(max_current_capabilities, max_current_1_8v, u8, 16, 23);
|
||||||
|
register_bits!(max_current_capabilities, max_current_3_0v, u8, 8, 15);
|
||||||
|
register_bits!(max_current_capabilities, max_current_3_3v, u8, 0, 7);
|
||||||
|
|
||||||
|
register!(force_event, ForceEvent, WO, u32);
|
||||||
|
register_bit!(force_event, ceata_error, 29);
|
||||||
|
register_bit!(force_event, target_response_error, 28);
|
||||||
|
register_bit!(force_event, adma_error, 25);
|
||||||
|
register_bit!(force_event, auto_cmd12_error, 24);
|
||||||
|
register_bit!(force_event, current_limit_error, 23);
|
||||||
|
register_bit!(force_event, data_end_bit_error, 22);
|
||||||
|
register_bit!(force_event, data_crc_error, 21);
|
||||||
|
register_bit!(force_event, data_timeout_error, 20);
|
||||||
|
register_bit!(force_event, cmd_index_error, 19);
|
||||||
|
register_bit!(force_event, cmd_end_bit_error, 18);
|
||||||
|
register_bit!(force_event, cmd_crc_error, 17);
|
||||||
|
register_bit!(force_event, cmd_timeout_error, 16);
|
||||||
|
register_bit!(force_event, cmd_not_issued_by_auto_cmd12_error, 7);
|
||||||
|
register_bit!(force_event, auto_cmd12_index_error, 4);
|
||||||
|
register_bit!(force_event, auto_cmd12_end_bit_error, 3);
|
||||||
|
register_bit!(force_event, auto_cmd12_crc_error, 2);
|
||||||
|
register_bit!(force_event, auto_cmd12_timeout_error, 1);
|
||||||
|
register_bit!(force_event, auto_cmd12_not_executed, 0);
|
||||||
|
|
||||||
|
register!(adma_error_status, AdmaErrorStatus, RW, u32, 0b11);
|
||||||
|
register_bit!(adma_error_status, length_mismatch_error, 2, WTC);
|
||||||
|
register_bits_typed!(adma_error_status, error_state, u8, AdmaErrorState, 0, 1);
|
||||||
|
|
||||||
|
register!(debug_selection, DebugSelection, WO, u32);
|
||||||
|
register_bit!(debug_selection, debug_select, 0);
|
||||||
|
|
||||||
|
register!(spi_interrupt_support, SpiInterruptSupport, RW, u32);
|
||||||
|
register_bits!(
|
||||||
|
spi_interrupt_support,
|
||||||
|
/// There should be a problem with the documentation of this field.
|
||||||
|
spi_int_support,
|
||||||
|
u8,
|
||||||
|
0,
|
||||||
|
7
|
||||||
|
);
|
||||||
|
|
||||||
|
register!(misc_reg, MiscReg, RO, u32);
|
||||||
|
register_bits!(misc_reg, vendor_version_num, u8, 24, 31);
|
||||||
|
register_bits_typed!(misc_reg, spec_ver, u8, SpecificationVersion, 16, 23);
|
||||||
|
register_bits!(
|
||||||
|
misc_reg,
|
||||||
|
/// Logical OR of interrupt signal and wakeup signal for each slot.
|
||||||
|
slot_interrupt_signal,
|
||||||
|
u8,
|
||||||
|
0,
|
||||||
|
7
|
||||||
|
);
|
||||||
|
|
@ -100,6 +100,19 @@ macro_rules! register_rw {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
);
|
);
|
||||||
|
($mod_name: ident, $struct_name: ident, $mask: expr) => (
|
||||||
|
impl libregister::RegisterRW for $struct_name {
|
||||||
|
#[inline]
|
||||||
|
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
|
||||||
|
unsafe {
|
||||||
|
self.inner.modify(|inner| {
|
||||||
|
f($mod_name::Read { inner }, $mod_name::Write { inner: inner & ($mask) })
|
||||||
|
.inner
|
||||||
|
});
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
#[doc(hidden)]
|
#[doc(hidden)]
|
||||||
|
|
@ -168,6 +181,14 @@ macro_rules! register {
|
||||||
libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
|
libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
|
||||||
libregister::register_vcell!($mod_name, $struct_name);
|
libregister::register_vcell!($mod_name, $struct_name);
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// Define read-write register with mask on write (for WTC mixed access.)
|
||||||
|
($mod_name: ident, $struct_name: ident, RW, $inner: ty, $mask: expr) => (
|
||||||
|
libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
|
||||||
|
libregister::register_r!($mod_name, $struct_name);
|
||||||
|
libregister::register_w!($mod_name, $struct_name);
|
||||||
|
libregister::register_rw!($mod_name, $struct_name, $mask);
|
||||||
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Define a 1-bit field of a register
|
/// Define a 1-bit field of a register
|
||||||
|
|
@ -197,6 +218,47 @@ macro_rules! register_bit {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// Single bit read-only
|
||||||
|
($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit: expr, RO) => (
|
||||||
|
$(#[$outer])*
|
||||||
|
impl $mod_name::Read {
|
||||||
|
#[allow(unused)]
|
||||||
|
#[inline]
|
||||||
|
pub fn $name(&self) -> bool {
|
||||||
|
use bit_field::BitField;
|
||||||
|
|
||||||
|
self.inner.get_bit($bit)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
);
|
||||||
|
|
||||||
|
// Single bit write to clear. Note that this must be used with WTC register.
|
||||||
|
($mod_name: ident, $(#[$outer:meta])* $name: ident, $bit: expr, WTC) => (
|
||||||
|
$(#[$outer])*
|
||||||
|
impl $mod_name::Read {
|
||||||
|
#[allow(unused)]
|
||||||
|
#[inline]
|
||||||
|
pub fn $name(&self) -> bool {
|
||||||
|
use bit_field::BitField;
|
||||||
|
|
||||||
|
self.inner.get_bit($bit)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
$(#[$outer])*
|
||||||
|
impl $mod_name::Write {
|
||||||
|
/// Clear bit field. (WTC)
|
||||||
|
#[allow(unused)]
|
||||||
|
#[inline]
|
||||||
|
pub fn $name(mut self) -> Self {
|
||||||
|
use bit_field::BitField;
|
||||||
|
|
||||||
|
self.inner.set_bit($bit, true);
|
||||||
|
self
|
||||||
|
}
|
||||||
|
}
|
||||||
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Define a multi-bit field of a register
|
/// Define a multi-bit field of a register
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue