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new target on pynqz2 and ps clk set to 50MHz #120

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missiannane wants to merge 1 commits from missiannane/zynq-rs-pynq-z2:master into master
pull from: missiannane/zynq-rs-pynq-z2:master
merge into: M-Labs:master
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libboard_zynq/src/clocks/source.rs
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@ -12,6 +12,8 @@ pub const PS_CLK: u32 = 33_333_333;
pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_kasli_soc")]
pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_pynqz2")]
pub const PS_CLK: u32 = 50_000_000;
/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[