libcortex_a9: add interrupt exit support for interrupt_handler macro #107
@ -56,10 +56,18 @@ extern "C" {
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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let id = gic.get_interrupt_id();
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match MPIDR.read().cpu_id(){
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0 => {
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if id.0 == 0 {
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println!("Interrupting core0...");
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gic.end_interrupt(id);
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return;
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}
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},
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1 => {
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if id.0 == 0 {
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if id.0 == 0 {
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gic.end_interrupt(id);
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gic.end_interrupt(id);
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asm::exit_irq();
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asm::exit_irq();
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@ -69,6 +77,8 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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notify_spin_lock();
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notify_spin_lock();
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main_core1();
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main_core1();
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}
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}
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},
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_ => {}
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}
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}
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stdio::drop_uart();
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stdio::drop_uart();
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println!("IRQ");
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println!("IRQ");
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@ -134,6 +144,10 @@ pub fn main_core0() {
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ddr.memtest();
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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ram::init_alloc_ddr(&mut ddr);
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info!("Send software interrupt to core0");
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core0.into());
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info!("Core0 returned from interrupt");
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boot::Core1::start(false);
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boot::Core1::start(false);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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@ -36,7 +36,9 @@ pub fn notify_spin_lock() {
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}
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}
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#[macro_export]
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#[macro_export]
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/// Interrupt handler, which setup the stack and jump to actual interrupt handler.
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/// Interrupt handler, which setup the stack and preserve registers before jumping to actual interrupt handler.
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/// Registers r0-r12, PC, SP and CPSR are restored after the actual handler.
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///
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/// - `name` is the name of the interrupt, should be the same as the one defined in vector table.
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/// - `name` is the name of the interrupt, should be the same as the one defined in vector table.
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/// - `name2` is the name for the actual handler, should be different from name.
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/// - `name2` is the name for the actual handler, should be different from name.
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/// - `stack0` is the stack for the interrupt handler when called from core0.
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/// - `stack0` is the stack for the interrupt handler when called from core0.
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@ -44,8 +46,7 @@ pub fn notify_spin_lock() {
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/// - `body` is the body of the actual interrupt handler, should be a normal unsafe rust function
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/// - `body` is the body of the actual interrupt handler, should be a normal unsafe rust function
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/// body.
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/// body.
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///
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///
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/// Note that the interrupt handler would use the same stack as normal programs by default, so
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/// Note that the interrupt handler would use the same stack as normal programs by default.
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/// interrupt handlers should not return to normal program or it may corrupt the stack.
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macro_rules! interrupt_handler {
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macro_rules! interrupt_handler {
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($name:ident, $name2:ident, $stack0:ident, $stack1:ident, $body:block) => {
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($name:ident, $name2:ident, $stack0:ident, $stack1:ident, $body:block) => {
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#[link_section = ".text.boot"]
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#[link_section = ".text.boot"]
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@ -54,19 +55,27 @@ macro_rules! interrupt_handler {
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pub unsafe extern "C" fn $name() -> ! {
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pub unsafe extern "C" fn $name() -> ! {
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asm!(
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asm!(
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// setup SP, depending on CPU 0 or 1
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// setup SP, depending on CPU 0 or 1
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// and preserve registers
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"sub lr, lr, #4",
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"stmfd sp!, {{r0-r12, lr}}",
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morgan marked this conversation as resolved
Outdated
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"mrc p15, #0, r0, c0, c0, #5",
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"mrc p15, #0, r0, c0, c0, #5",
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concat!("movw r1, :lower16:", stringify!($stack0)),
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concat!("movw r1, :lower16:", stringify!($stack0)),
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concat!("movt r1, :upper16:", stringify!($stack0)),
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concat!("movt r1, :upper16:", stringify!($stack0)),
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"tst r0, #3",
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"tst r0, #3",
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concat!("movwne r1, :lower16:", stringify!($stack1)),
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concat!("movwne r1, :lower16:", stringify!($stack1)),
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concat!("movtne r1, :upper16:", stringify!($stack1)),
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concat!("movtne r1, :upper16:", stringify!($stack1)),
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"mov r0, sp",
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"mov sp, r1",
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"mov sp, r1",
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"push {{r0, r1}}", // 2 registers are pushed to maintain 8 byte stack alignment
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sb10q
commented
Unclear what this "stack alignment" does exactly and why it is needed. Unclear what this "stack alignment" does exactly and why it is needed.
morgan
commented
The arm doc state the stack need to be 8 byte align and the easiest way to do it is to push/pop in multiple of 2 registers. When
The [arm doc](https://developer.arm.com/documentation/ddi0419/c/System-Level-Architecture/System-Level-Programmers--Model/ARMv6-M-exception-model/Stack-alignment-on-exception-entry?lang=en) state the stack need to be 8 byte align and the easiest way to do it is to push/pop in multiple of 2 registers.
When `push {{r0}}` is used with a timer interrupt, the wrpll satellite will result in the following error.
Which I suspect the compiler assume the stack pointer is 8 byte alignment and mess up the dellocation.
```bash
...
[ 0.000067s] INFO(satman): ARTIQ satellite manager starting...
[ 0.006019s] INFO(satman): gateware ident satellite
[ 0.016080s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 0.458796s] INFO(libboard_artiq::wrpll): Main Si549 started
[ 0.564532s] INFO(satman): Switching SYS clocks...
[ 0.619395s] INFO(satman): SYS CLK switched successfully
[ 0.921209s] INFO(libboard_artiq::wrpll): Helper Si549 started
[ 0.927196s] INFO(satman): uplink is up, switching to recovered clock
[ 0.933935s] INFO(libboard_artiq::wrpll): WRPLL started
[ 0.939230s] INFO(libboard_artiq::wrpll): warming up si549...
[ 20.945048s] INFO(libboard_artiq::wrpll): tracking gtx frequency...
[ 21.101694s] INFO(libboard_artiq::wrpll): starting helper PLL...
[ 21.468593s] INFO(libboard_artiq::wrpll): ...locked
[ 21.473541s] INFO(libboard_artiq::wrpll): starting main PLL interrupt...
[ 21.715075s] INFO(satman): TSC loaded from uplink
[ 21.724998s] INFO(satman): rank: 1
[ 21.728472s] INFO(satman): routing table: RoutingTable { 0: 0; 1: 1 0; 2: 2 0; 3: 3 0; 4: 4 0; }
[ 24.900000s] INFO(ksupport::irq): current count = 50000001 <---- interrupt prints
[ 29.880000s] INFO(ksupport::irq): current count = 60000001
[ 34.860000s] INFO(ksupport::irq): current count = 70000001
[ 36.263504s] INFO(satman): uplink is down, switching to local oscillator clock
[ 36.272139s] ERROR@�): received packet of an unknown type
[ 37.454274s] INFO@�): uplink is up, switching to recovered clock
[ 37.461085s] INFO(libboard_artiq::wrpll): WRPLL started
[ 37.466302s] INFO(libboard_artiq::wrpll): warming up si549...
[ 57.472198s] INFO(libboard_artiq::wrpll): tracking gtx frequency...
[ 57.628844s] INFO(libboard_artiq::wrpll): starting helper PLL...
[ 57.995403s] INFO(libboard_artiq::wrpll): ...locked
[ 58.000352s] INFO(libboard_artiq::wrpll): starting main PLL interrupt...
[ 58.296202s] INFO@�): TSC loaded from uplink
[ 58.306209s] INFO@�): rank: 1
[ 58.309682s] INFO@�): routing table: RoutingTable { 0: 0; 1: 1 0; 2: 2 0; 3: 3 0; 4: 4 0; }
[ 59.760001s] INFO(ksupport::irq): current count = 120000001
[ 64.740001s] INFO(ksupport::irq): current count = 130000001
[ 66.578307s] INFO@�): uplink is down, switching to local oscillator clock
Core 0 panic at /build/cargo-vendor-dir/linked_list_allocator-0.8.11/src/hole.rs:293:9: invalid deallocation (probably a double free)
```
sb10q
commented
Code comment needs to be expanded. Code comment needs to be expanded.
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concat!("bl ", stringify!($name2)),
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concat!("bl ", stringify!($name2)),
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"pop {{r0, r1}}",
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"mov sp, r0",
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"ldmfd sp!, {{r0-r12, pc}}^", // caret ^ : copy SPSR to the CPSR
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options(noreturn)
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options(noreturn)
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);
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);
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}
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}
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#[no_mangle]
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#[no_mangle]
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pub unsafe extern "C" fn $name2() -> ! $body
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pub unsafe extern "C" fn $name2() $body
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};
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};
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}
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}
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Reference in New Issue
Block a user
Nitpicking but the other instructions are lower-case.