add tcp listener

experiments/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
 default = ["target_zc706"]

experiments/src/main.rs

@@ -116,7 +116,6 @@ pub fn main_core0() {
 
     #[cfg(any(
         feature = "target_zc706",
-        feature = "target_ebaz4205",
         feature = "target_redpitaya",
         feature = "target_kasli_soc",
     ))]

flake.lock

@@ -1,12 +1,28 @@
 {
   "nodes": {
+    "mozilla-overlay": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1704373101,
+        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
+        "type": "github"
+      },
+      "original": {
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "type": "github"
+      }
+    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1731652201,
+        "lastModified": 1720386169,
-        "narHash": "sha256-XUO0JKP1hlww0d7mm3kpmIr4hhtR4zicg5Wwes9cPMg=",
+        "narHash": "sha256-NGKVY4PjzwAa4upkGtAMz1npHGoRzWotlSnVlqI40mo=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "c21b77913ea840f8bcf9adf4c41cecc2abffd38d",
+        "rev": "194846768975b7ad2c4988bdb82572c00222c0d7",
         "type": "github"
       },
       "original": {
@@ -18,29 +34,8 @@
     },
     "root": {
       "inputs": {
-        "nixpkgs": "nixpkgs",
+        "mozilla-overlay": "mozilla-overlay",
-        "rust-overlay": "rust-overlay"
+        "nixpkgs": "nixpkgs"
-      }
-    },
-    "rust-overlay": {
-      "inputs": {
-        "nixpkgs": [
-          "nixpkgs"
-        ]
-      },
-      "locked": {
-        "lastModified": 1719454714,
-        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
-        "owner": "oxalica",
-        "repo": "rust-overlay",
-        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
-        "type": "github"
-      },
-      "original": {
-        "owner": "oxalica",
-        "ref": "snapshot/2024-08-01",
-        "repo": "rust-overlay",
-        "type": "github"
       }
     }
   },

flake.nix

@@ -2,28 +2,29 @@
   description = "Bare-metal Rust on Zynq-7000";
 
   inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
-  inputs.rust-overlay = {
+  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
-    url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
-    inputs.nixpkgs.follows = "nixpkgs";
-  };
 
-  outputs = { self, nixpkgs, rust-overlay }:
+  outputs = { self, nixpkgs, mozilla-overlay }:
     let
-      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
+      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) crosspkgs-overlay ]; };
       
-      rust = pkgs.rust-bin.nightly."2021-01-28".default.override {
+      rustManifest = pkgs.fetchurl {
-        extensions = [ "rust-src" ];
+        url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
-        targets = [ ];
+        sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
       };
-      rustPlatform = pkgs.makeRustPlatform {
+      rustTargets = [];
-        rustc = rust // {
+      rustChannelOfTargets = _channel: _date: targets:
-          # https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
+        (pkgs.lib.rustLib.fromManifestFile rustManifest {
-          targetPlatforms = pkgs.lib.platforms.all;
+          inherit (pkgs) stdenv lib fetchurl patchelf;
-          tier1TargetPlatforms = pkgs.lib.platforms.all;
+          }).rust.override {
-          badTargetPlatforms = [ ];
+          inherit targets;
+          extensions = ["rust-src"];
         };
+      rust = rustChannelOfTargets "nightly" null rustTargets;
+      rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
+        rustc = rust;
         cargo = rust;
-      };
+      });
       
       # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
       llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
@@ -141,7 +142,7 @@
         "${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}";
         "${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}";
       };
-      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc" "ebaz4205"];
+      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
       allTargetCrates = (builtins.foldl' (results: target:
         results // targetCrates target
       ) {} targets);

libasync/src/smoltcp/tcp_stream.rs

@@ -19,6 +19,7 @@ use smoltcp::{
 use crate::task;
 use super::Sockets;
 
+
 /// References a smoltcp TcpSocket
 pub struct TcpStream {
     handle: SocketHandle,
@@ -281,6 +282,87 @@ impl Drop for TcpStream {
     }
 }
 
+// copied from artiq/runtime/sched.rs with modifications for async polling
+pub struct TcpListener {
+    handle: SocketHandle,
+    buffer_size: usize,
+    endpoint: IpEndpoint,
+}
+
+impl TcpListener {
+    fn new_socket_handle(buffer_size: usize) -> SocketHandle {
+        fn uninit_vec<T>(size: usize) -> Vec<T> {
+            let mut result = Vec::with_capacity(size);
+            unsafe {
+                result.set_len(size);
+            }
+            result
+        }
+        let rx_buffer = TcpSocketBuffer::new(uninit_vec(rx_bufsize));
+        let tx_buffer = TcpSocketBuffer::new(uninit_vec(tx_bufsize));
+        let socket = TcpSocket::new(rx_buffer, tx_buffer);
+        let handle = Sockets::instance().sockets.borrow_mut()
+            .add(socket);
+        handle
+    }
+
+    pub fn new(buffer_size: usize) -> TcpListener {
+        TcpListener {
+            handle: Self::new_socket_handle(buffer_size),
+            buffer_size,
+            endpoint: IpEndpoint::default(),
+        }
+    } 
+
+    fn with_lower<F, R>(&self, f: F) -> R
+    where
+        F: FnOnce(SocketRef<TcpSocket>) -> R,
+    {
+        let mut sockets = Sockets::instance().sockets.borrow_mut();
+        let mut socket_ref = sockets.get::<TcpSocket>(self.handle);
+        f(socket_ref)
+    }
+
+    pub fn can_accept(&self) -> bool {
+        self.with_lower(|s| s.is_active())
+    }
+
+    pub fn listen<T: Into<IpEndpoint>>(&self, endpoint: T) -> Result<(), Error> {
+        let endpoint = endpoint.into();
+        self.with_lower(|s| s.listen(endpoint))
+            .map(|| {
+                self.endpoint.set(endpoint)
+                ()
+            })
+            .map_err(|err| err.into())
+    }
+
+    pub async fn accept(&self) -> Result<TcpStream, Error> {
+        let handle = self.handle.get();
+
+        let stream = TcpStream { handle };
+
+        poll_stream!(&stream, (), |socket| {
+            if socket.state() != TcpState::Listen {
+                Poll::Ready(())
+            } else {
+                Poll::Pending
+            }
+        }).await;
+
+        self.handle.set(Self::new_lower(self.buffer_size.get()));
+        match self.listen(self.endpoint.get()) {
+            Ok(()) => (),
+            _ => unreachable!()
+        }
+        Ok(stream)
+    }
+
+    pub fn close(&self) {
+        self.with_lower(|mut s| s.close())
+    }
+}
+
 fn socket_is_handhshaking(socket: &SocketRef<TcpSocket>) -> bool {
     match socket.state() {
         TcpState::SynSent | TcpState::SynReceived =>

libboard_zynq/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = [ "smoltcp/proto-ipv6" ]

libboard_zynq/src/clocks/mod.rs

@@ -1,5 +1,3 @@
-use core::unimplemented;
-
 use libregister::{RegisterR, RegisterRW};
 use super::slcr;
 pub use slcr::ArmPllSource;
@@ -103,8 +101,6 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
         };
         pll / u32::from(uart_clk_ctrl.divisor())
     }
@@ -119,8 +115,6 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
         };
         pll / u32::from(sdio_clk_ctrl.divisor())
     }

libboard_zynq/src/clocks/source.rs

@@ -6,8 +6,6 @@ use super::slcr;
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_coraz7")]
 pub const PS_CLK: u32 = 50_000_000;
-#[cfg(feature = "target_ebaz4205")]
-pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_redpitaya")]
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_kasli_soc")]

libboard_zynq/src/ddr/mod.rs

@@ -16,10 +16,6 @@ const DDR_FREQ: u32 = 666_666_666;
 /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
 const DDR_FREQ: u32 = 525_000_000;
 
-#[cfg(feature = "target_ebaz4205")]
-/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
-const DDR_FREQ: u32 = 533_333_333;
-
 #[cfg(feature = "target_redpitaya")]
 /// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
 const DDR_FREQ: u32 = 533_333_333;
@@ -151,23 +147,22 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let data1_config = data0_config.clone();
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             let data0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::VrefDifferential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
+            let data1_config = slcr::DdriobConfig::zeroed()
-                feature = "target_ebaz4205",
+                .pullup_en(true);
-                feature = "target_redpitaya",
+            #[cfg(feature = "target_redpitaya")]
-                feature = "target_kasli_soc",
+            let data0_config = slcr::DdriobConfig::zeroed()
-            ))]
+                .inp_type(slcr::DdriobInputType::VrefDifferential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
             let data1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             slcr.ddriob_data0.write(data0_config);
@@ -181,23 +176,22 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let diff1_config = diff0_config.clone();
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             let diff0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::Differential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
+            let diff1_config = slcr::DdriobConfig::zeroed()
-                feature = "target_ebaz4205",
+                .pullup_en(true);
-                feature = "target_redpitaya",
+            #[cfg(feature = "target_redpitaya")]
-                feature = "target_kasli_soc",
+            let diff0_config = slcr::DdriobConfig::zeroed()
-            ))]
+                .inp_type(slcr::DdriobInputType::Differential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
             let diff1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             slcr.ddriob_diff0.write(diff0_config);
@@ -216,12 +210,7 @@ impl DdrRam {
                 slcr.ddriob_drive_slew_clock.write(0x00F9861C);
             }
 
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             slcr.ddriob_ddr_ctrl.modify(|_, w| w
                     .vref_int_en(false)
                     .vref_ext_en_lower(true)
@@ -235,6 +224,13 @@ impl DdrRam {
                     .vref_ext_en_lower(false)
                     .vref_ext_en_upper(false)
             );
+            #[cfg(feature = "target_redpitaya")]
+            slcr.ddriob_ddr_ctrl.modify(|_, w| w
+                    .vref_int_en(false)
+                    .vref_ext_en_lower(true)
+                    .vref_ext_en_upper(false)
+                    .refio_en(true)
+            );
         });
     }
 
@@ -246,13 +242,6 @@ impl DdrRam {
                 .t_rfc_min(0x9e)
                 .post_selfref_gap_x32(0x10)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param0.write(
-            regs::DramParam0::zeroed()
-                .t_rc(0x1a)
-                .t_rfc_min(0x56)
-                .post_selfref_gap_x32(0x10)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param0.write(
             regs::DramParam0::zeroed()
@@ -267,12 +256,6 @@ impl DdrRam {
                 .t_rfc_min(0x56)
                 .post_selfref_gap_x32(0x10)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param1.modify(
-            |_, w| w
-                .t_faw(0x16)
-                .t_ras_min(0x13)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param1.modify(
             |_, w| w
@@ -294,11 +277,6 @@ impl DdrRam {
                 .rd2pre(0x4)
                 .t_rcd(0x7)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param3.modify(
-            |_, w| w
-                .t_rp(7)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param3.modify(
             |_, w| w
@@ -320,21 +298,19 @@ impl DdrRam {
                 .emr(0x4)
         );
 
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
         self.regs.phy_configs[2].modify(
             |_, w| w.data_slice_in_use(false)
         );
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
+        self.regs.phy_configs[3].modify(
-            feature = "target_ebaz4205",
+            |_, w| w.data_slice_in_use(false)
-            feature = "target_redpitaya",
+        );
-            feature = "target_kasli_soc",
+        #[cfg(feature = "target_redpitaya")]
-        ))]
+        self.regs.phy_configs[2].modify(
+            |_, w| w.data_slice_in_use(false)
+        );
+        #[cfg(feature = "target_redpitaya")]
         self.regs.phy_configs[3].modify(
             |_, w| w.data_slice_in_use(false)
         );
@@ -378,11 +354,7 @@ impl DdrRam {
                 .gatelvl_init_ratio(0xee)
         );
 
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_kasli_soc"),
-        )]
         self.regs.reg_64.modify(
             |_, w| w
                 .phy_ctrl_slave_ratio(0x100)
@@ -418,12 +390,9 @@ impl DdrRam {
     fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
         #[cfg(feature = "target_zc706")]
         let width = regs::DataBusWidth::Width32bit;
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
+        let width = regs::DataBusWidth::Width16bit;
-            feature = "target_ebaz4205",
+        #[cfg(feature = "target_redpitaya")]
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
         let width = regs::DataBusWidth::Width16bit;
         self.regs.ddrc_ctrl.modify(|_, w| w
             .soft_rstb(false)
@@ -441,7 +410,6 @@ impl DdrRam {
         }
         #[cfg(any(
             feature = "target_coraz7",
-            feature = "target_ebaz4205",
             feature = "target_redpitaya",
             feature = "target_kasli_soc",
         ))]
@@ -482,8 +450,6 @@ impl DdrRam {
             feature = "target_kasli_soc",
         ))]
         let megabytes = 512;
-        #[cfg(feature = "target_ebaz4205")]
-        let megabytes = 256;
 
         megabytes * 1024 * 1024
     }

libboard_zynq/src/eth/mod.rs

@@ -65,31 +65,17 @@ impl Gem for Gem0 {
             slcr.gem0_clk_ctrl.write(
                 // 0x0050_0801: 8, 5: 100 Mb/s
                 // ...: 8, 1: 1000 Mb/s
-                #[cfg(not(feature = "target_ebaz4205"))]
                 slcr::GemClkCtrl::zeroed()
                     .clkact(true)
                     .srcsel(slcr::PllSource::IoPll)
                     .divisor(divisor0 as u8)
-                    .divisor1(divisor1 as u8),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
-                slcr::GemClkCtrl::zeroed()
-                    .clkact(true)
-                    .srcsel(slcr::PllSource::Emio)
-                    .divisor(divisor0 as u8)
                     .divisor1(divisor1 as u8)
             );
             // Enable gem0 recv clock
             slcr.gem0_rclk_ctrl.write(
                 // 0x0000_0801
-                #[cfg(not(feature = "target_ebaz4205"))]
-                slcr::RclkCtrl::zeroed()
-                    .clkact(true),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
                 slcr::RclkCtrl::zeroed()
                     .clkact(true)
-                    .srcsel(true)
             );
         });
     }
@@ -168,7 +154,6 @@ pub struct Eth<GEM: Gem, RX, TX> {
 
 impl Eth<Gem0, (), ()> {
     pub fn eth0(macaddr: [u8; 6]) -> Self {
-        #[cfg(not(feature = "target_ebaz4205"))]
         slcr::RegisterBlock::unlocked(|slcr| {
             // Manual example: 0x0000_1280
             // MDIO

libboard_zynq/src/eth/phy/mod.rs

@@ -83,7 +83,6 @@ pub struct Phy {
 const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
-const OUI_ICPLUS : u32 = 0x0090c3;
 
 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]
@@ -118,12 +117,6 @@ impl Phy {
                     model: 0,
                     ..
                 }) => true,
-                Some(PhyIdentifier {
-                    oui: OUI_ICPLUS,
-                    // IP101G-DS-R01
-                    model: 5,
-                    rev: 4,
-                }) => true,
                 _ => false,
             }
         }).map(|addr| Phy { addr })

libboard_zynq/src/eth/phy/status.rs

@@ -55,27 +55,7 @@ impl Status {
     pub fn get_link(&self) -> Option<Link> {
         if ! self.link_status() {
             None
-        } else if self.cap_100base_tx_full() {
+        } else if self.cap_10base_t_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_100base_tx_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_100base_t4() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_10base_t2_full() {
-            Some(Link {
-                speed: LinkSpeed::S10,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_10base_t2_half() {
             Some(Link {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Half,
@@ -85,11 +65,31 @@ impl Status {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Full,
             })
-        } else if self.cap_10base_t_half() {
+        } else if self.cap_10base_t2_half() {
             Some(Link {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Half,
             })
+        } else if self.cap_10base_t2_full() {
+            Some(Link {
+                speed: LinkSpeed::S10,
+                duplex: LinkDuplex::Full,
+            })
+        } else if self.cap_100base_t4() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_half() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_full() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Full,
+            })
         } else {
             None
         }

libboard_zynq/src/i2c/eeprom.rs

@@ -4,7 +4,6 @@ use embedded_hal::timer::CountDown;
 
 pub struct EEPROM<'a> {
     i2c: &'a mut I2c,
-    #[cfg(not(feature = "target_ebaz4205"))]
     port: u8,
     address: u8,
     page_size: u8,
@@ -47,11 +46,6 @@ impl<'a> EEPROM<'a> {
         Ok(())
     }
 
-    #[cfg(feature = "target_ebaz4205")]
-    fn select(&mut self) -> Result<(), &'static str> {
-        Ok(())
-    }
-
     /// Random read
     pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
         self.select()?;

libboard_zynq/src/i2c/mod.rs

@@ -2,13 +2,10 @@
 
 mod regs;
 pub mod eeprom;
-#[cfg(not(feature = "target_ebaz4205"))]
 use super::slcr;
 use super::time::Microseconds;
 use embedded_hal::timer::CountDown;
-use libregister::{RegisterR, RegisterRW};
+use libregister::{RegisterR, RegisterRW, RegisterW};
-#[cfg(not(feature = "target_ebaz4205"))]
-use libregister::RegisterW;
 #[cfg(feature = "target_kasli_soc")]
 use log::info;
 
@@ -25,10 +22,9 @@ pub struct I2c {
 }
 
 impl I2c {
-    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
     pub fn i2c0() -> Self {
         // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
-        #[cfg(not(feature = "target_ebaz4205"))]
         slcr::RegisterBlock::unlocked(|slcr| {
             // SCL
             slcr.mio_pin_50.write(

libboard_zynq/src/i2c/regs.rs

@@ -21,7 +21,6 @@ use libregister::{
 // Current compatibility:
 // zc706: GPIO 50, 51 == SCL, SDA
 // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
-// ebaz4205: GPIO (EMIO)
 
 pub struct RegisterBlock {
     pub gpio_output_mask: &'static mut GPIOOutputMask,
@@ -49,17 +48,17 @@ register!(gpio_output_mask,
           /// MASK_DATA_1_MSW:
           /// Maskable output data for MIO[53:48]
           GPIOOutputMask, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputMask, 0xE000A00C, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
               /// Output for SCL
               scl_o, 2);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
               /// Output for SDA
               sda_o, 3);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bits!(gpio_output_mask,
                /// Mask for keeping bits except SCL and SDA unchanged
                mask, u16, 16, 31);
@@ -83,13 +82,13 @@ register!(gpio_input,
           /// DATA_1_RO:
           /// Input data for MIO[53:32]
           GPIOInput, RO, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOInput, 0xE000A064, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
               /// Input for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
               /// Input for SDA
               sda, 19);
@@ -99,13 +98,13 @@ register!(gpio_direction,
           /// DIRM_1:
           /// Direction mode for MIO[53:32]; 0/1 = in/out
           GPIODirection, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIODirection, 0xE000A244, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
               /// Direction for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
               /// Direction for SDA
               sda, 19);
@@ -118,13 +117,13 @@ register!(gpio_output_enable,
           /// OEN_1:
           /// Output enable for MIO[53:32]
           GPIOOutputEnable, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputEnable, 0xE000A248, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
               /// Output enable for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
               /// Output enable for SDA
               sda, 19);

libboard_zynq/src/lib.rs

@@ -19,7 +19,7 @@ pub mod gic;
 pub mod time;
 pub mod timer;
 pub mod sdio;
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 pub mod i2c;
 pub mod logger;
 pub mod ps7_init;

libboard_zynq/src/sdio/mod.rs

@@ -116,8 +116,8 @@ impl Sdio {
                         .speed(true),
                 );
             }
-            // kasli_soc and redpitaya card detect pin
+            // redpitaya card detect pin
-            #[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
+            #[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
             {
                 unsafe {
                     slcr.sd0_wp_cd_sel.write(46 << 16);
@@ -128,20 +128,6 @@ impl Sdio {
                         .speed(true),
                 );
             }
-            // ebaz4205 card detect pin
-            #[cfg(feature = "target_ebaz4205")]
-            {
-                unsafe {
-                    slcr.sd0_wp_cd_sel.write(34 << 16);
-                }
-                slcr.mio_pin_34.write(
-                    slcr::MioPin34::zeroed()
-                        .io_type(slcr::IoBufferType::Lvcmos33)
-                        .pullup(true)
-                        .speed(true),
-                );
-            }
-
             slcr.sdio_rst_ctrl.reset_sdio0();
             slcr.aper_clk_ctrl.enable_sdio0();
             slcr.sdio_clk_ctrl.enable_sdio0();

libboard_zynq/src/slcr.rs

@@ -9,11 +9,9 @@ use libregister::{
 
 #[repr(u8)]
 pub enum PllSource {
-    IoPll  = 0b000,
+    IoPll  = 0b00,
-    ArmPll = 0b010,
+    ArmPll = 0b10,
-    DdrPll = 0b011,
+    DdrPll = 0b11,
-    // Ethernet controller 0 EMIO clock
-    Emio   = 0b100,
 }
 
 #[repr(u8)]

libboard_zynq/src/stdio.rs

@@ -47,11 +47,7 @@ impl DerefMut for LazyUart {
             LazyUart::Uninitialized => {
                 #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
                 let uart = Uart::uart0(UART_RATE);
-                #[cfg(any(
+                #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
-                    feature = "target_zc706",
-                    feature = "target_ebaz4205",
-                    feature = "target_kasli_soc",
-                ))]
                 let uart = Uart::uart1(UART_RATE);
                 *self = LazyUart::Initialized(uart);
                 self

libboard_zynq/src/uart/mod.rs

@@ -79,39 +79,6 @@ impl Uart {
         self_
     }
 
-    #[cfg(feature = "target_ebaz4205")]
-    pub fn uart1(baudrate: u32) -> Self {
-        slcr::RegisterBlock::unlocked(|slcr| {
-            // Route UART 1 RxD/TxD Signals to MIO Pins
-            // TX pin
-            slcr.mio_pin_24.write(
-                slcr::MioPin24::zeroed()
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-            // RX pin
-            slcr.mio_pin_25.write(
-                slcr::MioPin25::zeroed()
-                    .tri_enable(true)
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-        });
-
-        slcr::RegisterBlock::unlocked(|slcr| {
-            slcr.uart_rst_ctrl.reset_uart1();
-            slcr.aper_clk_ctrl.enable_uart1();
-            slcr.uart_clk_ctrl.enable_uart1();
-        });
-        let mut self_ = Uart {
-            regs: regs::RegisterBlock::uart1(),
-        };
-        self_.configure(baudrate);
-        self_
-    }
-
     pub fn write_byte(&mut self, value: u8) {
         while self.tx_fifo_full() {}
 

libconfig/Cargo.toml

@@ -13,7 +13,6 @@ log = "0.4"
 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = []

libconfig/src/net_settings.rs

@@ -59,10 +59,6 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
     let mut hardware_addr = get_address_from_eeprom();
     #[cfg(feature = "target_kasli_soc")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);
 
     if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
         hardware_addr = addr;

libsupport_zynq/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
 panic_handler = []

openocd/ebaz4205.cfg

@@ -1,33 +0,0 @@
-# The contents of this file are partially dependend on
-# the adapter that you have. Please modify accordingly.
-adapter driver ftdi
-ftdi vid_pid 0x0403 0x6010
-ftdi channel 0
-# Every pin set as high impedance except TCK, TDI, TDO and TMS
-ftdi layout_init 0x0088 0x008b
-
-# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
-# This choice is arbitrary. Use other GPIO pin if desired.
-ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
-
-transport select jtag
-adapter speed 10000
-
-set PL_TAPID 0x13722093
-set SMP 1
-
-source ./zynq-7000.cfg
-
-reset_config srst_only srst_open_drain
-adapter srst pulse_width 250
-adapter srst delay 400
-
-source ./common.cfg
-
-reset halt
-
-# Disable MMU
-targets $_TARGETNAME_1
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
-targets $_TARGETNAME_0
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]

szl/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
 default = ["target_zc706"]

szl/src/main.rs

@@ -80,15 +80,12 @@ pub fn main_core0() {
     );
     info!("Simple Zynq Loader starting...");
 
-    #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
+    #[cfg(not(feature = "target_kasli_soc"))]
     const CPU_FREQ: u32 = 800_000_000;
 
     #[cfg(feature = "target_kasli_soc")]
     const CPU_FREQ: u32 = 1_000_000_000;
 
-    #[cfg(feature = "target_ebaz4205")]
-    const CPU_FREQ: u32 = 666_666_666;
-
     ArmPll::setup(2 * CPU_FREQ);
     Clocks::set_cpu_freq(CPU_FREQ);
     IoPll::setup(1_000_000_000);