update flake lock

update cargo lock
core_io -> core2::io
2024-08-05 17:13:31 +08:00 · 2024-08-05 17:13:31 +08:00 · 2024-08-05 17:13:31 +08:00 · 2024-08-05 17:13:31 +08:00 · 2024-08-05 17:13:31 +08:00 · 2024-08-05 17:13:31 +08:00
41 changed files with 264 additions and 417 deletions
--- a/Cargo.lock
+++ b/Cargo.lock
@ -1,10 +1,12 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
+version = 3
+
 [[package]]
 name = "bit_field"
-version = "0.10.1"
+version = "0.10.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
+checksum = "dc827186963e592360843fb5ba4b973e145841266c1357f7180c43526f2e5b61"

 [[package]]
 name = "bitflags"
@ -14,9 +16,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"

 [[package]]
 name = "byteorder"
-version = "1.4.3"
+version = "1.3.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
+checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"

 [[package]]
 name = "cc"
@ -32,17 +34,17 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"

 [[package]]
 name = "compiler_builtins"
-version = "0.1.39"
+version = "0.1.49"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
+checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"

 [[package]]
-name = "core_io"
-version = "0.1.20210325"
+name = "core2"
+version = "0.3.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
+checksum = "2cf12d2dad3ed124aa116f59561428478993d69ab81ae4d30e5349c9c5b5a5f6"
 dependencies = [
- "rustc_version",
+ "memchr",
 ]

 [[package]]
@ -70,13 +72,12 @@ dependencies = [

 [[package]]
 name = "fatfs"
-version = "0.3.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
+version = "0.3.6"
+source = "git+https://github.com/SimonRenblad/rust-fatfs?branch=stable-0.3#6d935596a0d6faa19a4ca41b3db6de772d45c927"
 dependencies = [
 "bitflags",
 "byteorder",
- "core_io",
+ "core2",
 "log",
 ]

@ -111,7 +112,7 @@ dependencies = [
 name = "libconfig"
 version = "0.1.0"
 dependencies = [
- "core_io",
+ "core2",
 "fatfs",
 "libboard_zynq",
 "log",
@ -169,6 +170,12 @@ version = "0.7.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"

+[[package]]
+name = "memchr"
+version = "2.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2dffe52ecf27772e601905b7522cb4ef790d2cc203488bbd0e2fe85fcb74566d"
+
 [[package]]
 name = "nb"
 version = "0.1.3"
@ -196,21 +203,6 @@ version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"

-[[package]]
-name = "rustc_version"
-version = "0.1.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
-dependencies = [
- "semver",
-]
-
-[[package]]
-name = "semver"
-version = "0.1.20"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
-
 [[package]]
 name = "smoltcp"
 version = "0.7.5"
@ -227,7 +219,7 @@ name = "szl"
 version = "0.1.0"
 dependencies = [
 "byteorder",
- "core_io",
+ "core2",
 "libboard_zynq",
 "libconfig",
 "libcortex_a9",
@ -250,9 +242,9 @@ checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"

 [[package]]
 name = "volatile-register"
-version = "0.2.1"
+version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ee8f19f9d74293faf70901bc20ad067dc1ad390d2cbf1e3f75f721ffee908b6"
+checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
 dependencies = [
 "vcell",
 ]
--- a/experiments/Cargo.toml
+++ b/experiments/Cargo.toml
@ -3,18 +3,17 @@ name = "experiments"
 description = "Developing bare-metal Rust on Zynq"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
 default = ["target_zc706"]

 [dependencies]
-log = "0.4"
+log = "=0.4.14"
 embedded-hal = "0.2"
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }
--- a/experiments/src/main.rs
+++ b/experiments/src/main.rs
@ -1,12 +1,12 @@
 #![no_std]
 #![no_main]
-#![feature(const_in_array_repeat_expressions)]
 #![feature(naked_functions)]
 #![feature(asm)]

 extern crate alloc;

 use alloc::collections::BTreeMap;
+use core::arch::asm;
 use libasync::{
    delay,
    smoltcp::{Sockets, TcpStream},
@ -116,7 +116,6 @@ pub fn main_core0() {

    #[cfg(any(
        feature = "target_zc706",
-        feature = "target_ebaz4205",
        feature = "target_redpitaya",
        feature = "target_kasli_soc",
    ))]
--- a/flake.lock
+++ b/flake.lock
@ -2,11 +2,11 @@
  "nodes": {
    "nixpkgs": {
      "locked": {
-        "lastModified": 1731652201,
-        "narHash": "sha256-XUO0JKP1hlww0d7mm3kpmIr4hhtR4zicg5Wwes9cPMg=",
+        "lastModified": 1722651103,
+        "narHash": "sha256-IRiJA0NVAoyaZeKZluwfb2DoTpBAj+FLI0KfybBeDU0=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "c21b77913ea840f8bcf9adf4c41cecc2abffd38d",
+        "rev": "a633d89c6dc9a2a8aae11813a62d7c58b2c0cc51",
        "type": "github"
      },
      "original": {
--- a/flake.nix
+++ b/flake.nix
@ -2,6 +2,7 @@
  description = "Bare-metal Rust on Zynq-7000";

  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
+  #inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
  inputs.rust-overlay = {
    url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
    inputs.nixpkgs.follows = "nixpkgs";
@ -11,27 +12,37 @@
    let
      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
      
-      rust = pkgs.rust-bin.nightly."2021-01-28".default.override {
-        extensions = [ "rust-src" ];
-        targets = [ ];
-      };
-      rustPlatform = pkgs.makeRustPlatform {
-        rustc = rust // {
-          # https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
-          targetPlatforms = pkgs.lib.platforms.all;
-          tier1TargetPlatforms = pkgs.lib.platforms.all;
-          badTargetPlatforms = [ ];
-        };
-        cargo = rust;
-      };
+      # rustManifest = pkgs.fetchurl {
+      #   url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
+      #   sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
+      # };
+      # rustTargets = [];
+      # rustChannelOfTargets = _channel: _date: targets:
+      #   (pkgs.lib.rustLib.fromManifestFile rustManifest {
+      #     inherit (pkgs) stdenv lib fetchurl patchelf;
+      #     }).rust.override {
+      #     inherit targets;
+      #     extensions = ["rust-src"];
+      #   };
+      # rust = rustChannelOfTargets "nightly" null rustTargets;

+      # rustc version needs to match LLVM version, else ABI bugs
      # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
-      llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
-        inherit (pkgs.stdenvAdapters) overrideCC;
-        buildLlvmTools = null;
-        targetLlvmLibraries = null;
-        targetLlvm = null;
-      }));
+      rust = pkgs.rust-bin.nightly."2021-09-20".default.override {
+        extensions = [ "rust-src" ];
+      };
+      rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
+        rustc = rust;
+        cargo = rust;
+      });
+      
+      ## https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
+      #llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
+      #  inherit (pkgs.stdenvAdapters) overrideCC;
+      #  buildLlvmTools = null;
+      #  targetLlvmLibraries = null;
+      #  targetLlvm = null;
+      #}));

      crosspkgs-overlay = (self: super: {
        pkgsCross = super.pkgsCross // {
@ -103,9 +114,13 @@
        dontFixup = true;
      };

-      cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
-        postPatch = "substituteInPlace src/sysroot.rs --replace 2021 2018";
-      });
+      cargo-xbuild = pkgs.cargo-xbuild;
+      #cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
+      #  postPatch = "substituteInPlace src/sysroot.rs --replace 2021 2018";
+      #});
+      #cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
+      #  postPatch = "substituteInPlace src/sysroot.rs --replace 2023 2018";
+      #});

      build-crate = name: crate: features: rustPlatform.buildRustPackage rec {
        name = "${crate}";
@ -113,9 +128,15 @@
        src = builtins.filterSource (path: type:
          baseNameOf path != "target"
        ) ./.;
-        cargoLock = { lockFile = ./Cargo.lock; };

-        nativeBuildInputs = [ cargo-xbuild llvmPackages_11.clang-unwrapped ];
+        cargoLock = { 
+          lockFile = ./Cargo.lock;
+          outputHashes = {
+            "fatfs-0.3.6" = "sha256-guMlE0AjG9W9Fm4gUGghE5F1JA7IkV35fZAbYn+nb98=";
+          };
+        };
+
+        nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_13.clang-unwrapped ];
        buildPhase = ''
          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
@ -141,7 +162,7 @@
        "${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}";
        "${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}";
      };
-      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc" "ebaz4205"];
+      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
      allTargetCrates = (builtins.foldl' (results: target:
        results // targetCrates target
      ) {} targets);
@ -160,7 +181,7 @@

      hydraJobs = packages.x86_64-linux;

-      inherit rust rustPlatform llvmPackages_11;
+      inherit rust rustPlatform;

      devShell.x86_64-linux = pkgs.mkShell {
        name = "zynq-rs-dev-shell";
@ -171,7 +192,7 @@

          pkgs.openocd pkgs.gdb
          pkgs.openssh pkgs.rsync
-          llvmPackages_11.clang-unwrapped
+          pkgs.llvmPackages_13.clang-unwrapped
          (pkgs.python3.withPackages(ps: [ ps.pyftdi ]))
        ];
      };
--- a/libasync/Cargo.toml
+++ b/libasync/Cargo.toml
@ -3,7 +3,7 @@ name = "libasync"
 description = "low-level async support"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [dependencies]
 #futures = { version = "0.3", default-features = false }
--- a/libboard_zynq/Cargo.toml
+++ b/libboard_zynq/Cargo.toml
@ -3,12 +3,11 @@ name = "libboard_zynq"
 description = "Drivers for peripherals in the Zynq PS"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = [ "smoltcp/proto-ipv6" ]
@ -19,7 +18,7 @@ bit_field = "0.10"
 embedded-hal = "0.2"
 nb = "0.1"
 void = { version = "1", default-features = false }
-log = "0.4"
+log = "0.4.14"
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }
 libasync = { path = "../libasync" }
--- a/libboard_zynq/src/clocks/mod.rs
+++ b/libboard_zynq/src/clocks/mod.rs
@ -1,5 +1,3 @@
-use core::unimplemented;
-
 use libregister::{RegisterR, RegisterRW};
 use super::slcr;
 pub use slcr::ArmPllSource;
@ -103,8 +101,6 @@ impl Clocks {
                self.ddr,
            slcr::PllSource::IoPll =>
                self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
        };
        pll / u32::from(uart_clk_ctrl.divisor())
    }
@ -119,8 +115,6 @@ impl Clocks {
                self.ddr,
            slcr::PllSource::IoPll =>
                self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
        };
        pll / u32::from(sdio_clk_ctrl.divisor())
    }
--- a/libboard_zynq/src/clocks/source.rs
+++ b/libboard_zynq/src/clocks/source.rs
@ -6,8 +6,6 @@ use super::slcr;
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_coraz7")]
 pub const PS_CLK: u32 = 50_000_000;
-#[cfg(feature = "target_ebaz4205")]
-pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_redpitaya")]
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_kasli_soc")]
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@ -16,10 +16,6 @@ const DDR_FREQ: u32 = 666_666_666;
 /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
 const DDR_FREQ: u32 = 525_000_000;

-#[cfg(feature = "target_ebaz4205")]
-/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
-const DDR_FREQ: u32 = 533_333_333;
-
 #[cfg(feature = "target_redpitaya")]
 /// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
 const DDR_FREQ: u32 = 533_333_333;
@ -151,23 +147,22 @@ impl DdrRam {
                .output_en(slcr::DdriobOutputEn::Obuf);
            #[cfg(feature = "target_zc706")]
            let data1_config = data0_config.clone();
-            #[cfg(any(
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
            let data0_config = slcr::DdriobConfig::zeroed()
                .inp_type(slcr::DdriobInputType::VrefDifferential)
                .term_en(true)
                .dci_type(slcr::DdriobDciType::Termination)
                .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
+            let data1_config = slcr::DdriobConfig::zeroed()
+                .pullup_en(true);
+            #[cfg(feature = "target_redpitaya")]
+            let data0_config = slcr::DdriobConfig::zeroed()
+                .inp_type(slcr::DdriobInputType::VrefDifferential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
            let data1_config = slcr::DdriobConfig::zeroed()
                .pullup_en(true);
            slcr.ddriob_data0.write(data0_config);
@ -181,23 +176,22 @@ impl DdrRam {
                .output_en(slcr::DdriobOutputEn::Obuf);
            #[cfg(feature = "target_zc706")]
            let diff1_config = diff0_config.clone();
-            #[cfg(any(
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
            let diff0_config = slcr::DdriobConfig::zeroed()
                .inp_type(slcr::DdriobInputType::Differential)
                .term_en(true)
                .dci_type(slcr::DdriobDciType::Termination)
                .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
+            let diff1_config = slcr::DdriobConfig::zeroed()
+                .pullup_en(true);
+            #[cfg(feature = "target_redpitaya")]
+            let diff0_config = slcr::DdriobConfig::zeroed()
+                .inp_type(slcr::DdriobInputType::Differential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
            let diff1_config = slcr::DdriobConfig::zeroed()
                .pullup_en(true);
            slcr.ddriob_diff0.write(diff0_config);
@ -216,12 +210,7 @@ impl DdrRam {
                slcr.ddriob_drive_slew_clock.write(0x00F9861C);
            }

-            #[cfg(any(
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
            slcr.ddriob_ddr_ctrl.modify(|_, w| w
                    .vref_int_en(false)
                    .vref_ext_en_lower(true)
@ -235,6 +224,13 @@ impl DdrRam {
                    .vref_ext_en_lower(false)
                    .vref_ext_en_upper(false)
            );
+            #[cfg(feature = "target_redpitaya")]
+            slcr.ddriob_ddr_ctrl.modify(|_, w| w
+                    .vref_int_en(false)
+                    .vref_ext_en_lower(true)
+                    .vref_ext_en_upper(false)
+                    .refio_en(true)
+            );
        });
    }

@ -246,13 +242,6 @@ impl DdrRam {
                .t_rfc_min(0x9e)
                .post_selfref_gap_x32(0x10)
        );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param0.write(
-            regs::DramParam0::zeroed()
-                .t_rc(0x1a)
-                .t_rfc_min(0x56)
-                .post_selfref_gap_x32(0x10)
-        );
        #[cfg(feature = "target_redpitaya")]
        self.regs.dram_param0.write(
            regs::DramParam0::zeroed()
@ -267,12 +256,6 @@ impl DdrRam {
                .t_rfc_min(0x56)
                .post_selfref_gap_x32(0x10)
        );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param1.modify(
-            |_, w| w
-                .t_faw(0x16)
-                .t_ras_min(0x13)
-        );
        #[cfg(feature = "target_redpitaya")]
        self.regs.dram_param1.modify(
            |_, w| w
@ -294,11 +277,6 @@ impl DdrRam {
                .rd2pre(0x4)
                .t_rcd(0x7)
        );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param3.modify(
-            |_, w| w
-                .t_rp(7)
-        );
        #[cfg(feature = "target_redpitaya")]
        self.regs.dram_param3.modify(
            |_, w| w
@ -320,21 +298,19 @@ impl DdrRam {
                .emr(0x4)
        );

-        #[cfg(any(
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
        self.regs.phy_configs[2].modify(
            |_, w| w.data_slice_in_use(false)
        );
-        #[cfg(any(
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
+        self.regs.phy_configs[3].modify(
+            |_, w| w.data_slice_in_use(false)
+        );
+        #[cfg(feature = "target_redpitaya")]
+        self.regs.phy_configs[2].modify(
+            |_, w| w.data_slice_in_use(false)
+        );
+        #[cfg(feature = "target_redpitaya")]
        self.regs.phy_configs[3].modify(
            |_, w| w.data_slice_in_use(false)
        );
@ -378,11 +354,7 @@ impl DdrRam {
                .gatelvl_init_ratio(0xee)
        );

-        #[cfg(any(
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_kasli_soc"),
-        )]
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
        self.regs.reg_64.modify(
            |_, w| w
                .phy_ctrl_slave_ratio(0x100)
@ -418,12 +390,9 @@ impl DdrRam {
    fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
        #[cfg(feature = "target_zc706")]
        let width = regs::DataBusWidth::Width32bit;
-        #[cfg(any(
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
+        let width = regs::DataBusWidth::Width16bit;
+        #[cfg(feature = "target_redpitaya")]
        let width = regs::DataBusWidth::Width16bit;
        self.regs.ddrc_ctrl.modify(|_, w| w
            .soft_rstb(false)
@ -441,7 +410,6 @@ impl DdrRam {
        }
        #[cfg(any(
            feature = "target_coraz7",
-            feature = "target_ebaz4205",
            feature = "target_redpitaya",
            feature = "target_kasli_soc",
        ))]
@ -482,8 +450,6 @@ impl DdrRam {
            feature = "target_kasli_soc",
        ))]
        let megabytes = 512;
-        #[cfg(feature = "target_ebaz4205")]
-        let megabytes = 256;

        megabytes * 1024 * 1024
    }
--- a/libboard_zynq/src/eth/mod.rs
+++ b/libboard_zynq/src/eth/mod.rs
@ -65,31 +65,17 @@ impl Gem for Gem0 {
            slcr.gem0_clk_ctrl.write(
                // 0x0050_0801: 8, 5: 100 Mb/s
                // ...: 8, 1: 1000 Mb/s
-                #[cfg(not(feature = "target_ebaz4205"))]
                slcr::GemClkCtrl::zeroed()
                    .clkact(true)
                    .srcsel(slcr::PllSource::IoPll)
                    .divisor(divisor0 as u8)
-                    .divisor1(divisor1 as u8),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
-                slcr::GemClkCtrl::zeroed()
-                    .clkact(true)
-                    .srcsel(slcr::PllSource::Emio)
-                    .divisor(divisor0 as u8)
                    .divisor1(divisor1 as u8)
            );
            // Enable gem0 recv clock
            slcr.gem0_rclk_ctrl.write(
                // 0x0000_0801
-                #[cfg(not(feature = "target_ebaz4205"))]
-                slcr::RclkCtrl::zeroed()
-                    .clkact(true),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
                slcr::RclkCtrl::zeroed()
                    .clkact(true)
-                    .srcsel(true)
            );
        });
    }
@ -168,7 +154,6 @@ pub struct Eth<GEM: Gem, RX, TX> {

 impl Eth<Gem0, (), ()> {
    pub fn eth0(macaddr: [u8; 6]) -> Self {
-        #[cfg(not(feature = "target_ebaz4205"))]
        slcr::RegisterBlock::unlocked(|slcr| {
            // Manual example: 0x0000_1280
            // MDIO
--- a/libboard_zynq/src/eth/phy/mod.rs
+++ b/libboard_zynq/src/eth/phy/mod.rs
@ -83,7 +83,6 @@ pub struct Phy {
 const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
-const OUI_ICPLUS : u32 = 0x0090c3;

 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]
@ -118,12 +117,6 @@ impl Phy {
                    model: 0,
                    ..
                }) => true,
-                Some(PhyIdentifier {
-                    oui: OUI_ICPLUS,
-                    // IP101G-DS-R01
-                    model: 5,
-                    rev: 4,
-                }) => true,
                _ => false,
            }
        }).map(|addr| Phy { addr })
--- a/libboard_zynq/src/eth/phy/status.rs
+++ b/libboard_zynq/src/eth/phy/status.rs
@ -55,27 +55,7 @@ impl Status {
    pub fn get_link(&self) -> Option<Link> {
        if ! self.link_status() {
            None
-        } else if self.cap_100base_tx_full() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_100base_tx_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_100base_t4() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_10base_t2_full() {
-            Some(Link {
-                speed: LinkSpeed::S10,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_10base_t2_half() {
+        } else if self.cap_10base_t_half() {
            Some(Link {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Half,
@ -85,11 +65,31 @@ impl Status {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Full,
            })
-        } else if self.cap_10base_t_half() {
+        } else if self.cap_10base_t2_half() {
            Some(Link {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Half,
            })
+        } else if self.cap_10base_t2_full() {
+            Some(Link {
+                speed: LinkSpeed::S10,
+                duplex: LinkDuplex::Full,
+            })
+        } else if self.cap_100base_t4() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_half() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_full() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Full,
+            })
        } else {
            None
        }
--- a/libboard_zynq/src/i2c/eeprom.rs
+++ b/libboard_zynq/src/i2c/eeprom.rs
@ -4,7 +4,6 @@ use embedded_hal::timer::CountDown;

 pub struct EEPROM<'a> {
    i2c: &'a mut I2c,
-    #[cfg(not(feature = "target_ebaz4205"))]
    port: u8,
    address: u8,
    page_size: u8,
@ -47,11 +46,6 @@ impl<'a> EEPROM<'a> {
        Ok(())
    }

-    #[cfg(feature = "target_ebaz4205")]
-    fn select(&mut self) -> Result<(), &'static str> {
-        Ok(())
-    }
-
    /// Random read
    pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
        self.select()?;
--- a/libboard_zynq/src/i2c/mod.rs
+++ b/libboard_zynq/src/i2c/mod.rs
@ -2,13 +2,10 @@

 mod regs;
 pub mod eeprom;
-#[cfg(not(feature = "target_ebaz4205"))]
 use super::slcr;
 use super::time::Microseconds;
 use embedded_hal::timer::CountDown;
-use libregister::{RegisterR, RegisterRW};
-#[cfg(not(feature = "target_ebaz4205"))]
-use libregister::RegisterW;
+use libregister::{RegisterR, RegisterRW, RegisterW};
 #[cfg(feature = "target_kasli_soc")]
 use log::info;

@ -25,10 +22,9 @@ pub struct I2c {
 }

 impl I2c {
-    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
    pub fn i2c0() -> Self {
        // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
-        #[cfg(not(feature = "target_ebaz4205"))]
        slcr::RegisterBlock::unlocked(|slcr| {
            // SCL
            slcr.mio_pin_50.write(
--- a/libboard_zynq/src/i2c/regs.rs
+++ b/libboard_zynq/src/i2c/regs.rs
@ -21,7 +21,6 @@ use libregister::{
 // Current compatibility:
 // zc706: GPIO 50, 51 == SCL, SDA
 // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
-// ebaz4205: GPIO (EMIO)

 pub struct RegisterBlock {
    pub gpio_output_mask: &'static mut GPIOOutputMask,
@ -49,17 +48,17 @@ register!(gpio_output_mask,
          /// MASK_DATA_1_MSW:
          /// Maskable output data for MIO[53:48]
          GPIOOutputMask, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputMask, 0xE000A00C, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
              /// Output for SCL
              scl_o, 2);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
              /// Output for SDA
              sda_o, 3);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bits!(gpio_output_mask,
               /// Mask for keeping bits except SCL and SDA unchanged
               mask, u16, 16, 31);
@ -83,13 +82,13 @@ register!(gpio_input,
          /// DATA_1_RO:
          /// Input data for MIO[53:32]
          GPIOInput, RO, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOInput, 0xE000A064, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
              /// Input for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
              /// Input for SDA
              sda, 19);
@ -99,13 +98,13 @@ register!(gpio_direction,
          /// DIRM_1:
          /// Direction mode for MIO[53:32]; 0/1 = in/out
          GPIODirection, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIODirection, 0xE000A244, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
              /// Direction for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
              /// Direction for SDA
              sda, 19);
@ -118,13 +117,13 @@ register!(gpio_output_enable,
          /// OEN_1:
          /// Output enable for MIO[53:32]
          GPIOOutputEnable, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputEnable, 0xE000A248, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
              /// Output enable for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
              /// Output enable for SDA
              sda, 19);
--- a/libboard_zynq/src/lib.rs
+++ b/libboard_zynq/src/lib.rs
@ -19,7 +19,7 @@ pub mod gic;
 pub mod time;
 pub mod timer;
 pub mod sdio;
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 pub mod i2c;
 pub mod logger;
 pub mod ps7_init;
--- a/libboard_zynq/src/sdio/mod.rs
+++ b/libboard_zynq/src/sdio/mod.rs
@ -116,8 +116,8 @@ impl Sdio {
                        .speed(true),
                );
            }
-            // kasli_soc and redpitaya card detect pin
-            #[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
+            // redpitaya card detect pin
+            #[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
            {
                unsafe {
                    slcr.sd0_wp_cd_sel.write(46 << 16);
@ -128,20 +128,6 @@ impl Sdio {
                        .speed(true),
                );
            }
-            // ebaz4205 card detect pin
-            #[cfg(feature = "target_ebaz4205")]
-            {
-                unsafe {
-                    slcr.sd0_wp_cd_sel.write(34 << 16);
-                }
-                slcr.mio_pin_34.write(
-                    slcr::MioPin34::zeroed()
-                        .io_type(slcr::IoBufferType::Lvcmos33)
-                        .pullup(true)
-                        .speed(true),
-                );
-            }
-
            slcr.sdio_rst_ctrl.reset_sdio0();
            slcr.aper_clk_ctrl.enable_sdio0();
            slcr.sdio_clk_ctrl.enable_sdio0();
--- a/libboard_zynq/src/slcr.rs
+++ b/libboard_zynq/src/slcr.rs
@ -9,11 +9,9 @@ use libregister::{

 #[repr(u8)]
 pub enum PllSource {
-    IoPll  = 0b000,
-    ArmPll = 0b010,
-    DdrPll = 0b011,
-    // Ethernet controller 0 EMIO clock
-    Emio   = 0b100,
+    IoPll  = 0b00,
+    ArmPll = 0b10,
+    DdrPll = 0b11,
 }

 #[repr(u8)]
--- a/libboard_zynq/src/stdio.rs
+++ b/libboard_zynq/src/stdio.rs
@ -47,11 +47,7 @@ impl DerefMut for LazyUart {
            LazyUart::Uninitialized => {
                #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
                let uart = Uart::uart0(UART_RATE);
-                #[cfg(any(
-                    feature = "target_zc706",
-                    feature = "target_ebaz4205",
-                    feature = "target_kasli_soc",
-                ))]
+                #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
                let uart = Uart::uart1(UART_RATE);
                *self = LazyUart::Initialized(uart);
                self
--- a/libboard_zynq/src/uart/mod.rs
+++ b/libboard_zynq/src/uart/mod.rs
@ -79,39 +79,6 @@ impl Uart {
        self_
    }

-    #[cfg(feature = "target_ebaz4205")]
-    pub fn uart1(baudrate: u32) -> Self {
-        slcr::RegisterBlock::unlocked(|slcr| {
-            // Route UART 1 RxD/TxD Signals to MIO Pins
-            // TX pin
-            slcr.mio_pin_24.write(
-                slcr::MioPin24::zeroed()
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-            // RX pin
-            slcr.mio_pin_25.write(
-                slcr::MioPin25::zeroed()
-                    .tri_enable(true)
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-        });
-
-        slcr::RegisterBlock::unlocked(|slcr| {
-            slcr.uart_rst_ctrl.reset_uart1();
-            slcr.aper_clk_ctrl.enable_uart1();
-            slcr.uart_clk_ctrl.enable_uart1();
-        });
-        let mut self_ = Uart {
-            regs: regs::RegisterBlock::uart1(),
-        };
-        self_.configure(baudrate);
-        self_
-    }
-
    pub fn write_byte(&mut self, value: u8) {
        while self.tx_fifo_full() {}

--- a/libconfig/Cargo.toml
+++ b/libconfig/Cargo.toml
@ -2,19 +2,17 @@
 name = "libconfig"
 version = "0.1.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [dependencies]
 libboard_zynq = { path = "../libboard_zynq" }
-core_io = { version = "0.1", features = ["collections"] }
-fatfs = { version = "0.3", features = ["core_io"], default-features = false }
-log = "0.4"
+core2 = { version = "=0.3.2", features = ["alloc", "nightly"], default-features = false }
+fatfs = { git = "https://github.com/SimonRenblad/rust-fatfs", branch = "stable-0.3", features = ["core2", "alloc"], default-features = false }
+log = "=0.4.14"

 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = []
-fat_lfn = [ "fatfs/alloc" ]
--- a/libconfig/src/bootgen.rs
+++ b/libconfig/src/bootgen.rs
@ -1,5 +1,5 @@
 use alloc::vec::Vec;
-use core_io::{Error, Read, Seek, SeekFrom};
+use core2::io::{Error, Read, Seek, SeekFrom};
 use libboard_zynq::devc;
 use log::debug;

--- a/libconfig/src/lib.rs
+++ b/libconfig/src/lib.rs
@ -3,7 +3,7 @@ extern crate alloc;

 use core::fmt;
 use alloc::{string::FromUtf8Error, string::String, vec::Vec, rc::Rc};
-use core_io::{self as io, BufRead, BufReader, Read, Write, Seek, SeekFrom};
+use core2::io::{self as io, Read, Write, Seek, SeekFrom};
 use libboard_zynq::sdio;

 pub mod sd_reader;
@ -54,11 +54,13 @@ impl<'a> From<FromUtf8Error> for Error<'a> {
 fn parse_config<'a>(
    key: &'a str,
    buffer: &mut Vec<u8>,
-    file: fatfs::File<sd_reader::SdReader>,
+    file: &mut fatfs::File<sd_reader::SdReader>,
 ) -> Result<'a, ()> {
    let prefix = [key, "="].concat().to_ascii_lowercase();
-    for line in BufReader::new(file).lines() {
-        let line = line?.to_ascii_lowercase();
+    let mut read_buf = Vec::new();
+    file.read_to_end(&mut read_buf)?;
+    for line in String::from_utf8(read_buf)?.lines() {
+        let line = line.to_ascii_lowercase();
        if line.starts_with(&prefix) {
            buffer.extend(line[prefix.len()..].as_bytes());
            return Ok(());
@ -101,7 +103,7 @@ impl Config {
            match root_dir.open_file(&["/CONFIG/", key, ".BIN"].concat()) {
                Ok(mut f) => f.read_to_end(&mut buffer).map(|_| ())?,
                Err(_) => match root_dir.open_file("/CONFIG.TXT") {
-                    Ok(f) => parse_config(key, &mut buffer, f)?,
+                    Ok(mut f) => parse_config(key, &mut buffer, &mut f)?,
                    Err(_) => return Err(Error::KeyNotFoundError(key)),
                },
            };
@ -124,11 +126,11 @@ impl Config {
                    let prefix = [key, "="].concat().to_ascii_lowercase();
                    match root_dir.create_file("/CONFIG.TXT") {
                        Ok(mut f) => {
-                            let mut buffer = String::new();
-                            f.read_to_string(&mut buffer)?;
+                            let mut buffer = Vec::new();
+                            f.read_to_end(&mut buffer)?;
                            f.seek(SeekFrom::Start(0))?;
                            f.truncate()?;
-                            for line in buffer.lines() {
+                            for line in String::from_utf8(buffer)?.lines() {
                                if line.len() > 0 && !line.to_ascii_lowercase().starts_with(&prefix) {
                                    f.write(line.as_bytes())?;
                                    f.write(NEWLINE)?;
--- a/libconfig/src/net_settings.rs
+++ b/libconfig/src/net_settings.rs
@ -59,10 +59,6 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
    let mut hardware_addr = get_address_from_eeprom();
    #[cfg(feature = "target_kasli_soc")]
    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);

    if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
        hardware_addr = addr;
--- a/libconfig/src/sd_reader.rs
+++ b/libconfig/src/sd_reader.rs
@ -1,4 +1,4 @@
-use core_io::{BufRead, Error, ErrorKind, Read, Result as IoResult, Seek, SeekFrom, Write};
+use core2::io::{BufRead, Error, ErrorKind, Read, Result as IoResult, Seek, SeekFrom, Write};
 use fatfs;
 use libboard_zynq::sdio::{sd_card::SdCard, CmdTransferError};
 use log::debug;
--- a/libcortex_a9/Cargo.toml
+++ b/libcortex_a9/Cargo.toml
@ -2,7 +2,7 @@
 name = "libcortex_a9"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [features]
 power_saving = []
--- a/libcortex_a9/src/asm.rs
+++ b/libcortex_a9/src/asm.rs
@ -1,59 +1,60 @@
+use core::arch::asm;
+
 /// The classic no-op
 #[inline]
 pub fn nop() {
-    unsafe { llvm_asm!("nop" :::: "volatile") }
+    unsafe { asm!("nop") }
 }

 /// Wait For Event
 #[inline]
 pub fn wfe() {
-    unsafe { llvm_asm!("wfe" :::: "volatile") }
+    unsafe { asm!("wfe") }
 }

 /// Send Event
 #[inline]
 pub fn sev() {
-    unsafe { llvm_asm!("sev" :::: "volatile") }
+    unsafe { asm!("sev") }
 }

 /// Data Memory Barrier
 #[inline]
 pub fn dmb() {
-    unsafe { llvm_asm!("dmb" :::: "volatile") }
+    unsafe { asm!("dmb") }
 }

 /// Data Synchronization Barrier
 #[inline]
 pub fn dsb() {
-    unsafe { llvm_asm!("dsb" :::: "volatile") }
+    unsafe { asm!("dsb") }
 }

 /// Instruction Synchronization Barrier
 #[inline]
 pub fn isb() {
-    unsafe { llvm_asm!("isb" :::: "volatile") }
+    unsafe { asm!("isb") }
 }

 /// Enable FIQ
 #[inline]
 pub unsafe fn enable_fiq() {
-    llvm_asm!("cpsie f":::: "volatile");
+    asm!("cpsie f");
 }

 /// Enable IRQ
 #[inline]
 pub unsafe fn enable_irq() {
-    llvm_asm!("cpsie i":::: "volatile");
+    asm!("cpsie i");
 }

 /// Disable IRQ, return if IRQ was originally enabled.
 #[inline]
 pub unsafe fn enter_critical() -> bool {
    let mut cpsr: u32;
-    llvm_asm!(
-        "mrs $0, cpsr
-         cpsid i"
-         : "=r"(cpsr) ::: "volatile");
+    asm!(
+        "mrs {}, cpsr
+         cpsid i", out(reg) cpsr);
    (cpsr & (1 << 7)) == 0
 }

@ -65,18 +66,18 @@ pub unsafe fn exit_critical(enable: bool) {
    } else {
        0
    };
-    llvm_asm!(
+    asm!(
        "mrs r1, cpsr
-         bic r1, r1, $0
+         bic r1, r1, {}
         msr cpsr_c, r1"
-         :: "r"(mask) : "r1");
+         , in(reg) mask);
 }

 /// Exiting IRQ
 #[inline]
 pub unsafe fn exit_irq() {
-    llvm_asm!("
+    asm!("
        mrs r0, SPSR
        msr CPSR, r0
-        " ::: "r0");
+        ");
 }
--- a/libcortex_a9/src/cache.rs
+++ b/libcortex_a9/src/cache.rs
@ -1,11 +1,12 @@
 use super::asm::{dmb, dsb};
 use super::l2c::*;
+use core::arch::asm;

 /// Invalidate TLBs
 #[inline(always)]
 pub fn tlbiall() {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0);
    }
 }

@ -13,7 +14,7 @@ pub fn tlbiall() {
 #[inline(always)]
 pub fn iciallu() {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0);
    }
 }

@ -21,7 +22,7 @@ pub fn iciallu() {
 #[inline(always)]
 pub fn bpiall() {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0);
    }
 }

@ -29,7 +30,7 @@ pub fn bpiall() {
 #[inline(always)]
 pub fn dccsw(setway: u32) {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway);
    }
 }

@ -41,7 +42,7 @@ pub fn dcisw(setway: u32) {
        // also see example code (for DCCISW, but DCISW will be
        // analogous) "Example code for cache maintenance operations"
        // on pages B2-1286 and B2-1287.
-        llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway);
    }
 }

@ -49,7 +50,7 @@ pub fn dcisw(setway: u32) {
 #[inline(always)]
 pub fn dccisw(setway: u32) {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway);
    }
 }

@ -69,7 +70,7 @@ pub fn dciall_l1() {

    // select L1 data cache
    unsafe {
-        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
    }

    // Invalidate entire D-Cache by iterating every set and every way
@ -104,7 +105,7 @@ pub fn dcciall_l1() {

    // select L1 data cache
    unsafe {
-        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
    }

    // Invalidate entire D-Cache by iterating every set and every way
@ -156,7 +157,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
 #[inline(always)]
 pub fn dccimvac(addr: usize) {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr);
    }
 }

@ -198,10 +199,9 @@ pub fn dcci_slice<T>(slice: &[T]) {
 #[inline(always)]
 pub fn dccmvac(addr: usize) {
    unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr);
    }
 }
-
 /// Data cache clean for an object.
 pub fn dcc<T>(object: &T) {
    dmb();
@ -239,7 +239,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
 /// affecting more data than intended.
 #[inline(always)]
 pub unsafe fn dcimvac(addr: usize) {
-    llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
+    asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr);
 }

 /// Data cache clean and invalidate for an object.
--- a/libcortex_a9/src/fpu.rs
+++ b/libcortex_a9/src/fpu.rs
@ -1,7 +1,8 @@
+use core::arch::asm;
 /// Enable FPU in the current core.
 pub fn enable_fpu() {
    unsafe {
-        llvm_asm!("
+        asm!("
            mrc p15, 0, r1, c1, c0, 2
            orr r1, r1, (0b1111<<20)
            mcr p15, 0, r1, c1, c0, 2
@ -9,6 +10,6 @@ pub fn enable_fpu() {
            vmrs r1, fpexc
            orr r1, r1, (1<<30)
            vmsr fpexc, r1
-            ":::"r1");
+            ");
    }
 }
--- a/libcortex_a9/src/lib.rs
+++ b/libcortex_a9/src/lib.rs
@ -1,7 +1,7 @@
 #![no_std]
-#![feature(llvm_asm, global_asm)]
 #![feature(never_type)]
-#![feature(const_fn)]
+#![feature(asm, global_asm)]
+#![feature(const_fn_trait_bound)]

 extern crate alloc;

@ -17,6 +17,7 @@ pub mod sync_channel;
 mod uncached;
 pub use fpu::enable_fpu;
 pub use uncached::UncachedSlice;
+use core::arch::global_asm;

 global_asm!(include_str!("exceptions.s"));

--- a/libcortex_a9/src/regs.rs
+++ b/libcortex_a9/src/regs.rs
@ -2,6 +2,7 @@ use libregister::{
    register_bit, register_bits,
    RegisterR, RegisterW, RegisterRW,
 };
+use core::arch::asm;

 macro_rules! def_reg_r {
    ($name:tt, $type: ty, $asm_instr:tt) => {
@ -11,7 +12,7 @@ macro_rules! def_reg_r {
            #[inline]
            fn read(&self) -> Self::R {
                let mut value: u32;
-                unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
+                unsafe { asm!($asm_instr, out(reg) value) }
                value.into()
            }
        }
@ -26,7 +27,7 @@ macro_rules! def_reg_w {
            #[inline]
            fn write(&mut self, value: Self::W) {
                let value: u32 = value.into();
-                unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
+                unsafe { asm!($asm_instr, in(reg) value) }
            }

            #[inline]
@ -71,29 +72,29 @@ macro_rules! wrap_reg {

 /// Stack Pointer
 pub struct SP;
-def_reg_r!(SP, u32, "mov $0, sp");
-def_reg_w!(SP, u32, "mov sp, $0");
+def_reg_r!(SP, u32, "mov {}, sp");
+def_reg_w!(SP, u32, "mov sp, {}");

 /// Link register (function call return address)
 pub struct LR;
-def_reg_r!(LR, u32, "mov $0, lr");
-def_reg_w!(LR, u32, "mov lr, $0");
+def_reg_r!(LR, u32, "mov {}, lr");
+def_reg_w!(LR, u32, "mov lr, {}");

 pub struct VBAR;
-def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
-def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
+def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
+def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");

 pub struct MVBAR;
-def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
-def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
+def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
+def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");

 pub struct HVBAR;
-def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
-def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
+def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
+def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");

 /// Multiprocess Affinity Register
 pub struct MPIDR;
-def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
+def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
 wrap_reg!(mpidr);
 register_bits!(mpidr,
               /// CPU core index
@ -106,15 +107,15 @@ register_bit!(mpidr,
              u, 30);

 pub struct DFAR;
-def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
+def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");

 pub struct DFSR;
-def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
+def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");

 pub struct SCTLR;
 wrap_reg!(sctlr);
-def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
-def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
+def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
+def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
 register_bit!(sctlr,
              /// Enables MMU
              m, 0);
@ -147,8 +148,8 @@ register_bit!(sctlr,
 /// Auxiliary Control Register
 pub struct ACTLR;
 wrap_reg!(actlr);
-def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
-def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
+def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
+def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
 // SMP bit
 register_bit!(actlr, parity_on, 9);
 register_bit!(actlr, alloc_one_way, 8);
@ -183,17 +184,17 @@ impl ACTLR {

 /// Domain Access Control Register
 pub struct DACR;
-def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
-def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
+def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
+def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");

 /// Translation Table Base Register 0
 pub struct TTBR0;
 /// Translation Table Base Register 1
 pub struct TTBR1;
-def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
-def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
-def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
-def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
+def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
+def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
+def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
+def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
 wrap_reg!(ttbr);
 register_bits!(ttbr, table_base, u32, 14, 31);
 register_bit!(ttbr, irgn0, 6);
--- a/libcortex_a9/src/sync_channel.rs
+++ b/libcortex_a9/src/sync_channel.rs
@ -178,7 +178,8 @@ macro_rules! sync_channel {
        {
            use core::sync::atomic::{AtomicUsize, AtomicPtr};
            use $crate::sync_channel::{Sender, Receiver};
-            static LIST: [AtomicPtr<$t>; $cap + 1] = [AtomicPtr::new(core::ptr::null_mut()); $cap + 1];
+            const cnst_ptr: AtomicPtr<$t> = AtomicPtr::new(core::ptr::null_mut());
+            static LIST: [AtomicPtr<$t>; $cap + 1] = [cnst_ptr; $cap + 1];
            static WRITE: AtomicUsize = AtomicUsize::new(0);
            static READ: AtomicUsize = AtomicUsize::new(0);
            (Sender::new(&LIST, &WRITE, &READ), Receiver::new(&LIST, &WRITE, &READ))
--- a/libregister/Cargo.toml
+++ b/libregister/Cargo.toml
@ -2,7 +2,7 @@
 name = "libregister"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [dependencies]
 vcell = "0.1"
--- a/libsupport_zynq/Cargo.toml
+++ b/libsupport_zynq/Cargo.toml
@ -3,12 +3,11 @@ name = "libsupport_zynq"
 description = "Software support for running in the Zynq PS"
 version = "0.0.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [features]
 target_zc706 = ["libboard_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
 panic_handler = []
@ -20,11 +19,11 @@ default = ["panic_handler", "dummy_irq_handler", "dummy_fiq_handler"]

 [dependencies]
 r0 = "1"
-compiler_builtins = "=0.1.39"
+compiler_builtins = "=0.1.49"
 linked_list_allocator = { version = "0.8", default-features = false, features = ["const_mut_refs"] }
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }
 libboard_zynq = { path = "../libboard_zynq" }

 [build-dependencies]
-cc = { version = "1.0" }
+cc = { version = "=1.0.73" }
--- a/libsupport_zynq/src/boot.rs
+++ b/libsupport_zynq/src/boot.rs
@ -1,5 +1,6 @@
 use r0::zero_bss;
 use core::ptr::write_volatile;
+use core::arch::asm;
 use libregister::{
    VolatileCell,
    RegisterR, RegisterRW,
--- a/libsupport_zynq/src/exception_vectors.rs
+++ b/libsupport_zynq/src/exception_vectors.rs
@ -1,6 +1,7 @@
 use libregister::{RegisterR, RegisterW};
 use libcortex_a9::{regs::{DFSR, MPIDR, VBAR}, interrupt_handler};
 use libboard_zynq::{println, stdio}; 
+use core::arch::asm;

 pub fn set_vector_table(base_addr: u32){
    VBAR.write(base_addr);
--- a/openocd/ebaz4205.cfg
+++ b/openocd/ebaz4205.cfg
@ -1,33 +0,0 @@
-# The contents of this file are partially dependend on
-# the adapter that you have. Please modify accordingly.
-adapter driver ftdi
-ftdi vid_pid 0x0403 0x6010
-ftdi channel 0
-# Every pin set as high impedance except TCK, TDI, TDO and TMS
-ftdi layout_init 0x0088 0x008b
-
-# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
-# This choice is arbitrary. Use other GPIO pin if desired.
-ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
-
-transport select jtag
-adapter speed 10000
-
-set PL_TAPID 0x13722093
-set SMP 1
-
-source ./zynq-7000.cfg
-
-reset_config srst_only srst_open_drain
-adapter srst pulse_width 250
-adapter srst delay 400
-
-source ./common.cfg
-
-reset halt
-
-# Disable MMU
-targets $_TARGETNAME_1
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
-targets $_TARGETNAME_0
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
--- a/szl/Cargo.toml
+++ b/szl/Cargo.toml
@ -3,20 +3,19 @@ name = "szl"
 description = "Simple Zynq Loader"
 version = "0.1.0"
 authors = ["M-Labs"]
-edition = "2018"
+edition = "2021"

 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
 default = ["target_zc706"]

 [dependencies]
-log = "0.4"
-byteorder = { version = "1.3", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
+log = "=0.4.14"
+byteorder = { version = "=1.3", default-features = false }
+core2 = { version = "=0.3.2", default-features = false, features = ["alloc", "nightly"] }

 libboard_zynq = { path = "../libboard_zynq" }
 libsupport_zynq = { path = "../libsupport_zynq" }
--- a/szl/src/main.rs
+++ b/szl/src/main.rs
@ -8,7 +8,7 @@ mod netboot;

 use alloc::rc::Rc;
 use core::mem;
-use core_io::{Read, Seek};
+use core2::io::{Read, Seek};
 use libboard_zynq::{
    self as zynq,
    clocks::source::{ArmPll, ClockSource, IoPll},
@ -80,15 +80,12 @@ pub fn main_core0() {
    );
    info!("Simple Zynq Loader starting...");

-    #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
+    #[cfg(not(feature = "target_kasli_soc"))]
    const CPU_FREQ: u32 = 800_000_000;

    #[cfg(feature = "target_kasli_soc")]
    const CPU_FREQ: u32 = 1_000_000_000;

-    #[cfg(feature = "target_ebaz4205")]
-    const CPU_FREQ: u32 = 666_666_666;
-
    ArmPll::setup(2 * CPU_FREQ);
    Clocks::set_cpu_freq(CPU_FREQ);
    IoPll::setup(1_000_000_000);
--- a/szl/src/netboot.rs
+++ b/szl/src/netboot.rs
@ -1,7 +1,7 @@
 use alloc::vec;
 use alloc::vec::Vec;
 use byteorder::{ByteOrder, NetworkEndian};
-use core_io::{Read, Seek};
+use core2::io::{Read, Seek};
 use libboard_zynq::{
    devc,
    eth::Eth,
Author	SHA1	Message	Date
Simon Renblad	ef27cf0a5d	update flake lock	2024-08-05 17:13:31 +08:00
Simon Renblad	09460c4c7e	update cargo lock	2024-08-05 17:13:31 +08:00
Simon Renblad	26bde04a19	core_io -> core2::io	2024-08-05 17:13:31 +08:00
Simon Renblad	313662b196	compiler, cc, log deps	2024-08-05 17:13:31 +08:00
Simon Renblad	57604acf93	update version	2024-08-05 17:13:31 +08:00
Simon Renblad	4980ec1c6f	llvm_asm -> asm	2024-08-05 17:13:31 +08:00
Simon Renblad	1307297583	update flake	2024-08-05 17:13:31 +08:00