Cargo.lock

@@ -1,7 +1,5 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
-
 [[package]]
 name = "bit_field"
 version = "0.10.1"
@@ -16,9 +14,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
 
 [[package]]
 name = "byteorder"
-version = "1.3.0"
+version = "1.4.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "60f0b0d4c0a382d2734228fd12b5a6b5dac185c60e938026fd31b265b94f9bd2"
+checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
 
 [[package]]
 name = "cc"
@@ -34,14 +32,18 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "compiler_builtins"
-version = "0.1.49"
+version = "0.1.39"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
+checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
 
 [[package]]
 name = "core_io"
-version = "0.1.0"
+version = "0.1.20210325"
-source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
+dependencies = [
+ "rustc_version",
+]
 
 [[package]]
 name = "embedded-hal"
@@ -68,8 +70,9 @@ dependencies = [
 
 [[package]]
 name = "fatfs"
-version = "0.3.6"
+version = "0.3.5"
-source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -193,6 +196,21 @@ version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
 
+[[package]]
+name = "rustc_version"
+version = "0.1.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
+dependencies = [
+ "semver",
+]
+
+[[package]]
+name = "semver"
+version = "0.1.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
+
 [[package]]
 name = "smoltcp"
 version = "0.7.5"

armv7-none-eabihf.json

@@ -1,4 +1,12 @@
 {
+  "abi-blacklist": [
+    "stdcall",
+    "fastcall",
+    "vectorcall",
+    "thiscall",
+    "win64",
+    "sysv64"
+  ],
   "arch": "arm",
   "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
   "emit-debug-gdb-scripts": false,

experiments/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
 default = ["target_zc706"]
@@ -19,5 +18,5 @@ embedded-hal = "0.2"
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }
 libboard_zynq = { path = "../libboard_zynq" }
-libsupport_zynq = { path = "../libsupport_zynq", default-features = false, features = ["panic_handler", "dummy_fiq_handler"]}
+libsupport_zynq = { path = "../libsupport_zynq", default-features = false, features = ["panic_handler"]}
 libasync = { path = "../libasync" }

experiments/src/main.rs

@@ -1,14 +1,12 @@
 #![no_std]
 #![no_main]
-#![allow(incomplete_features)]
+#![feature(const_in_array_repeat_expressions)]
 #![feature(naked_functions)]
 #![feature(asm)]
-#![feature(inline_const)]
 
 extern crate alloc;
 
 use alloc::collections::BTreeMap;
-use core::arch::asm;
 use libasync::{
     delay,
     smoltcp::{Sockets, TcpStream},
@@ -41,7 +39,7 @@ use libcortex_a9::{
 };
 use libregister::{RegisterR, RegisterW};
 use libsupport_zynq::{
-    boot, exception_vectors, ram,
+    boot, ram,
 };
 use log::{info, warn};
 use core::sync::atomic::{AtomicBool, Ordering};
@@ -58,29 +56,19 @@ extern "C" {
 static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
 
 interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
-    let mpcore = mpcore::RegisterBlock::mpcore();
+    if MPIDR.read().cpu_id() == 1{
-    let mut gic = gic::InterruptController::gic(mpcore);
+        let mpcore = mpcore::RegisterBlock::mpcore();
-    let id = gic.get_interrupt_id();
+        let mut gic = gic::InterruptController::gic(mpcore);
-    match MPIDR.read().cpu_id(){
+        let id = gic.get_interrupt_id();
-        0 => {
+        if id.0 == 0 {
-            if id.0 == 0 {
+            gic.end_interrupt(id);
-                println!("Interrupting core0...");
+            asm::exit_irq();
-                gic.end_interrupt(id);
+            SP.write(&mut __stack1_start as *mut _ as u32);
-                return;
+            asm::enable_irq();
-            }
+            CORE1_RESTART.store(false, Ordering::Relaxed);
-        },
+            notify_spin_lock();
-        1 => {
+            main_core1();
-            if id.0 == 0 {
+        }
-                gic.end_interrupt(id);
-                asm::exit_irq();
-                SP.write(&mut __stack1_start as *mut _ as u32);
-                asm::enable_irq();
-                CORE1_RESTART.store(false, Ordering::Relaxed);
-                notify_spin_lock();
-                main_core1();
-            }
-        },
-        _ => {}
     }
     stdio::drop_uart();
     println!("IRQ");
@@ -98,7 +86,6 @@ pub fn restart_core1() {
 
 #[no_mangle]
 pub fn main_core0() {
-    exception_vectors::set_vector_table(0x0);
     // zynq::clocks::CpuClocks::enable_io(1_250_000_000);
     enable_l2_cache(0x8);
     println!("\nZynq experiments");
@@ -118,7 +105,6 @@ pub fn main_core0() {
 
     #[cfg(any(
         feature = "target_zc706",
-        feature = "target_ebaz4205",
         feature = "target_redpitaya",
         feature = "target_kasli_soc",
     ))]
@@ -148,10 +134,6 @@ pub fn main_core0() {
     ddr.memtest();
     ram::init_alloc_ddr(&mut ddr);
 
-    info!("Send software interrupt to core0");
-    interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core0.into());
-    info!("Core0 returned from interrupt");
-
     boot::Core1::start(false);
 
     let core1_req = unsafe { &mut CORE1_REQ.0 };
@@ -201,20 +183,6 @@ pub fn main_core0() {
         println!("");
     }
 
-    #[cfg(feature = "target_kasli_soc")]
-    {
-        let mut err_cdwn = timer.countdown();
-        let mut err_state = true;
-        let mut led = zynq::error_led::ErrorLED::error_led();
-        task::spawn( async move { 
-            loop {
-                led.toggle(err_state);
-                err_state = !err_state;
-                delay(&mut err_cdwn, Milliseconds(1000)).await;
-            }
-        });
-    }
-
     let eth = zynq::eth::Eth::eth0(HWADDR.clone());
     println!("Eth on");
 

flake.lock

@@ -1,46 +1,41 @@
 {
   "nodes": {
+    "mozilla-overlay": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1650459918,
+        "narHash": "sha256-sroCK+QJTmoXtcRkwZyKOP9iAYOPID2Bwdxn4GkG16w=",
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "rev": "e1f7540fc0a8b989fb8cf701dc4fd7fc76bcf168",
+        "type": "github"
+      },
+      "original": {
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "type": "github"
+      }
+    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1734529975,
+        "lastModified": 1653920503,
-        "narHash": "sha256-ze3IJksru9dN0keqUxY0WNf8xrwfs8Ty/z9v/keyBbg=",
+        "narHash": "sha256-BBeCZwZImtjP3oYy4WogkQYy5OxNyfNciVSc1AfZgLQ=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "72d11d40b9878a67c38f003c240c2d2e1811e72a",
+        "rev": "a634c8f6c1fbf9b9730e01764999666f3436f10a",
         "type": "github"
       },
       "original": {
         "owner": "NixOS",
-        "ref": "nixos-24.05",
+        "ref": "nixos-22.05",
         "repo": "nixpkgs",
         "type": "github"
       }
     },
     "root": {
       "inputs": {
-        "nixpkgs": "nixpkgs",
+        "mozilla-overlay": "mozilla-overlay",
-        "rust-overlay": "rust-overlay"
+        "nixpkgs": "nixpkgs"
-      }
-    },
-    "rust-overlay": {
-      "inputs": {
-        "nixpkgs": [
-          "nixpkgs"
-        ]
-      },
-      "locked": {
-        "lastModified": 1719454714,
-        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
-        "owner": "oxalica",
-        "repo": "rust-overlay",
-        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
-        "type": "github"
-      },
-      "original": {
-        "owner": "oxalica",
-        "ref": "snapshot/2024-08-01",
-        "repo": "rust-overlay",
-        "type": "github"
       }
     }
   },

flake.nix

@@ -1,53 +1,173 @@
 {
   description = "Bare-metal Rust on Zynq-7000";
 
-  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-22.05;
-  inputs.rust-overlay = {
+  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
-    url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
-    inputs.nixpkgs.follows = "nixpkgs";
-  };
 
-  outputs = { self, nixpkgs, rust-overlay }:
+  outputs = { self, nixpkgs, mozilla-overlay }:
     let
-      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
+      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
       
-      rust = pkgs.rust-bin.nightly."2021-09-01".default.override {
+      rustManifest = pkgs.fetchurl {
-        extensions = [ "rust-src" ];
+        url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
-        targets = [ ];
+        sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
       };
-      rustPlatform = pkgs.makeRustPlatform {
+      rustTargets = [];
-        rustc = rust // {
+      rustChannelOfTargets = _channel: _date: targets:
-          # https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
+        (pkgs.lib.rustLib.fromManifestFile rustManifest {
-          targetPlatforms = pkgs.lib.platforms.all;
+          inherit (pkgs) stdenv lib fetchurl patchelf;
-          tier1TargetPlatforms = pkgs.lib.platforms.all;
+          }).rust.override {
-          badTargetPlatforms = [ ];
+          inherit targets;
+          extensions = ["rust-src"];
         };
+      rust = rustChannelOfTargets "nightly" null rustTargets;
+      rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
+        rustc = rust;
         cargo = rust;
+      });
+
+      gnu-platform = "arm-none-eabi";
+
+      binutils-pkg = { zlib, extraConfigureFlags ? [] }: pkgs.stdenv.mkDerivation rec {
+        basename = "binutils";
+        version = "2.30";
+        name = "${basename}-${gnu-platform}-${version}";
+        src = pkgs.fetchurl {
+          url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
+          sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
+        };
+        configureFlags = [
+          "--enable-deterministic-archives"
+          "--target=${gnu-platform}"
+          "--with-cpu=cortex-a9"
+          "--with-fpu=vfpv3"
+          "--with-float=hard"
+          "--with-mode=thumb"
+        ] ++ extraConfigureFlags;
+        outputs = [ "out" "info" "man" ];
+        depsBuildBuild = [ pkgs.buildPackages.stdenv.cc ];
+        buildInputs = [ zlib ];
+        enableParallelBuilding = true;
+        meta = {
+          description = "Tools for manipulating binaries (linker, assembler, etc.)";
+          longDescription = ''
+            The GNU Binutils are a collection of binary tools.  The main
+            ones are `ld' (the GNU linker) and `as' (the GNU assembler).
+            They also include the BFD (Binary File Descriptor) library,
+            `gprof', `nm', `strip', etc.
+          '';
+          homepage = http://www.gnu.org/software/binutils/;
+          license = pkgs.lib.licenses.gpl3Plus;
+          /* Give binutils a lower priority than gcc-wrapper to prevent a
+            collision due to the ld/as wrappers/symlinks in the latter. */
+          priority = "10";
+        };
       };
 
-      crosspkgs-overlay = (self: super: {
+      gcc-pkg = { gmp, mpfr, libmpc, platform-binutils, extraConfigureFlags ? [] }: pkgs.stdenv.mkDerivation rec {
-        pkgsCross = super.pkgsCross // {
+        basename = "gcc";
-          zynq-baremetal = import super.path {
+        version = "9.1.0";
-            system = "x86_64-linux";
+        name = "${basename}-${gnu-platform}-${version}";
-            crossSystem = {
+        src = pkgs.fetchurl {
-              config = "arm-none-eabihf";
+          url = "https://ftp.gnu.org/gnu/gcc/gcc-${version}/gcc-${version}.tar.xz";
-              libc = "newlib";
+          sha256 = "1817nc2bqdc251k0lpc51cimna7v68xjrnvqzvc50q3ax4s6i9kr";
-              gcc.cpu = "cortex-a9";
-              gcc.fpu = "vfpv3";
-            };
-          };
         };
-      });
+        preConfigure = ''
+          mkdir build
+          cd build
+        '';
+        configureScript = "../configure";
+        configureFlags = [ 
+          "--target=${gnu-platform}"
+          "--with-arch=armv7-a"
+          "--with-tune=cortex-a9"
+          "--with-fpu=vfpv3"
+          "--with-float=hard"
+          "--disable-libssp"
+          "--enable-languages=c"
+          "--with-as=${platform-binutils}/bin/${gnu-platform}-as"
+          "--with-ld=${platform-binutils}/bin/${gnu-platform}-ld" ] ++ extraConfigureFlags;
+        outputs = [ "out" "info" "man" ];
+        hardeningDisable = [ "format" "pie" ];
+        propagatedBuildInputs = [ gmp mpfr libmpc platform-binutils ];
+        enableParallelBuilding = true;
+        dontFixup = true;
+      };
+
+      newlib-pkg = { platform-binutils, platform-gcc }: pkgs.stdenv.mkDerivation rec {
+        pname = "newlib";
+        version = "3.1.0";
+        src = pkgs.fetchurl {
+          url = "ftp://sourceware.org/pub/newlib/newlib-${version}.tar.gz";
+          sha256 = "0ahh3n079zjp7d9wynggwrnrs27440aac04340chf1p9476a2kzv";
+        };
+        nativeBuildInputs = [ platform-binutils platform-gcc ];
+        configureFlags = [
+          "--target=${gnu-platform}"
+
+          "--with-cpu=cortex-a9"
+          "--with-fpu=vfpv3"
+          "--with-float=hard"
+          "--with-mode=thumb"
+          "--enable-interwork"
+          "--disable-multilib"
+
+          "--disable-newlib-supplied-syscalls"
+          "--with-gnu-ld"
+          "--with-gnu-as"
+          "--disable-newlib-io-float"
+          "--disable-werror"
+        ];
+        dontFixup = true;
+      };
+      gnutoolchain = rec {
+        binutils-bootstrap = pkgs.callPackage binutils-pkg { };
+        gcc-bootstrap = pkgs.callPackage gcc-pkg {
+          platform-binutils = binutils-bootstrap;
+          extraConfigureFlags = [ "--disable-libgcc" ];
+        };
+        newlib = pkgs.callPackage newlib-pkg {
+          platform-binutils = binutils-bootstrap;
+          platform-gcc = gcc-bootstrap;
+        };
+        binutils = pkgs.callPackage binutils-pkg {
+          extraConfigureFlags = [ "--with-lib-path=${newlib}/arm-none-eabi/lib" ];
+        };
+        gcc = pkgs.callPackage gcc-pkg {
+          platform-binutils = binutils;
+          extraConfigureFlags = [ "--enable-newlib" "--with-headers=${newlib}/arm-none-eabi/include" ];
+        };
+      };
+
+      cargo-xbuild = rustPlatform.buildRustPackage rec {
+        pname = "cargo-xbuild";
+        version = "0.6.5";
+
+        src = pkgs.fetchFromGitHub {
+          owner = "rust-osdev";
+          repo = pname;
+          rev = "v${version}";
+          sha256 = "18djvygq9v8rmfchvi2hfj0i6fhn36m716vqndqnj56fiqviwxvf";
+        };
+        cargoSha256 = "13sj9j9kl6js75h9xq0yidxy63vixxm9q3f8jil6ymarml5wkhx8";
+
+        meta = with pkgs.lib; {
+          description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
+          homepage = "https://github.com/rust-osdev/cargo-xbuild";
+          license = with licenses; [ mit asl20 ];
+          maintainers = with maintainers; [ johntitor xrelkd ];
+        };
+      };
 
       mkbootimage = pkgs.stdenv.mkDerivation {
         pname = "mkbootimage";
-        version = "2.3dev";
+        version = "2.2";
 
         src = pkgs.fetchFromGitHub {
           owner = "antmicro";
           repo = "zynq-mkbootimage";
-          rev = "872363ce32c249f8278cf107bc6d3bdeb38d849f";
+          rev = "4ee42d782a9ba65725ed165a4916853224a8edf7";
-          sha256 = "sha256-5FPyAhUWZDwHbqmp9J2ZXTmjaXPz+dzrJMolaNwADHs=";
+          sha256 = "1k1mbsngqadqihzjgvwvsrkvryxy5ladpxd9yh9iqn2s7fxqwqa9";
         };
 
         propagatedBuildInputs = [ pkgs.libelf pkgs.pcre ];
@@ -60,7 +180,6 @@
           mkdir -p $out/bin
           cp mkbootimage $out/bin
         '';
-        hardeningDisable = [ "fortify" ];
       };
 
       fsbl = { board ? "zc706" }: pkgs.stdenv.mkDerivation {
@@ -68,20 +187,19 @@
         src = pkgs.fetchFromGitHub {
           owner = "Xilinx";
           repo = "embeddedsw";
-          rev = "xilinx_v2022.2";
+          rev = "65c849ed46c88c67457e1fc742744f96db968ff1";
-          sha256 = "sha256-UDz9KK/Hw3qM1BAeKif30rE8Bi6C2uvuZlvyvtJCMfw=";
+          sha256 = "1rvl06ha40dzd6s9aa4sylmksh4xb9dqaxq462lffv1fdk342pda";
         };
+        patches = [ ./fsbl.patch ];
         nativeBuildInputs = [
-          pkgs.pkgsCross.zynq-baremetal.buildPackages.binutils
+          pkgs.gnumake
-          pkgs.pkgsCross.zynq-baremetal.buildPackages.gcc
+          gnutoolchain.binutils
+          gnutoolchain.gcc
         ];
         patchPhase = ''
+          patch -p1 -i ${./fsbl.patch}
           patchShebangs lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh
-
+          echo 'SEARCH_DIR("${gnutoolchain.newlib}/arm-none-eabi/lib");' >> lib/sw_apps/zynq_fsbl/src/lscript.ld
-          for x in lib/sw_apps/zynq_fsbl/src/Makefile lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh lib/bsp/standalone/src/arm/cortexa9/gcc/Makefile; do
-            substituteInPlace $x \
-              --replace "arm-none-eabi-" "arm-none-eabihf-"
-          done
         '';
         buildPhase = ''
           cd lib/sw_apps/zynq_fsbl/src
@@ -95,27 +213,17 @@
         dontFixup = true;
       };
 
-      cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
-        postPatch = "substituteInPlace src/sysroot.rs --replace 2021 2018";
-      });
-
       build-crate = name: crate: features: rustPlatform.buildRustPackage rec {
         name = "${crate}";
 
         src = builtins.filterSource (path: type:
           baseNameOf path != "target"
         ) ./.;
-        cargoLock = { 
+        cargoLock = { lockFile = ./Cargo.lock; };
-          lockFile = ./Cargo.lock;
-          outputHashes = {
-            "core_io-0.1.0" = "sha256-0HINFWRiJx8pjMgUOL/CS336ih7SENSRh3Kah9LPRrw="; 
-            "fatfs-0.3.6" = "sha256-Nz9hCq/1YgSXF8ltJ5ZawV0Hc8WV44KNK0tJdVnNb4U=";
-          };
-        };
 
-        nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_13.clang-unwrapped ];
+        nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_9.clang-unwrapped ];
         buildPhase = ''
-          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
+          export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
           pushd ${crate}
           cargo xbuild --release --frozen \
@@ -132,14 +240,13 @@
 
         doCheck = false;
         dontFixup = true;
-        auditable = false;
       };
 
       targetCrates = target: {
         "${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}";
         "${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}";
       };
-      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc" "ebaz4205"];
+      targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
       allTargetCrates = (builtins.foldl' (results: target:
         results // targetCrates target
       ) {} targets);
@@ -158,20 +265,21 @@
 
       hydraJobs = packages.x86_64-linux;
 
-      inherit rust rustPlatform;
+      inherit rustPlatform;
 
       devShell.x86_64-linux = pkgs.mkShell {
         name = "zynq-rs-dev-shell";
-        buildInputs = [
+        buildInputs = with pkgs; [
-          rust
+          rustPlatform.rust.rustc
+          rustPlatform.rust.cargo
+          cacert
           cargo-xbuild
-          mkbootimage
 
-          pkgs.openocd pkgs.gdb
+          openocd gdb
-          pkgs.openssh pkgs.rsync
+          openssh rsync
-          pkgs.llvmPackages_13.clang-unwrapped
+          llvmPackages_9.clang-unwrapped
-          (pkgs.python3.withPackages(ps: [ ps.pyftdi ]))
+          (python3.withPackages(ps: [ ps.pyftdi ]))
-        ];
+          mkbootimage ];
-      };
+        };
     };
-}
+}

fsbl.patch

@@ -0,0 +1,31 @@
+diff --git a/lib/sw_apps/zynq_fsbl/src/Makefile b/lib/sw_apps/zynq_fsbl/src/Makefile
+index 0e3ccdf1c5..a5b02f386e 100644
+--- a/lib/sw_apps/zynq_fsbl/src/Makefile
++++ b/lib/sw_apps/zynq_fsbl/src/Makefile
+@@ -71,11 +71,14 @@ endif
+ all: $(EXEC)
+ 
+ $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
+-	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
+ 	$(LINKER) $(LD1FLAGS)  -o $@ $(OBJS) $(LDFLAGS)
+ 	rm -rf $(OBJS)
+-	
+-	
++
++.PHONY: ps7_init
++
++ps7_init:
++	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
++
+ $(LIBS): 
+ 	echo "Copying BSP files"
+ 	$(BSP_DIR)/copy_bsp.sh $(BOARD) $(CC)
+@@ -86,7 +89,7 @@ $(LIBS):
+         make -C $(BSP_DIR) -k all "CC=armcc" "AR=armar" "C_FLAGS= -O2 -c" "EC_FLAGS=--debug --wchar32"; \
+ 	fi;
+ 
+-%.o:%.c
++%.o:%.c ps7_init
+ 	$(CC) $(CC_FLAGS) $(CFLAGS) $(ECFLAGS) -c $< -o $@ $(INCLUDEPATH)
+ 
+ %.o:%.S

libboard_zynq/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = [ "smoltcp/proto-ipv6" ]

libboard_zynq/src/clocks/mod.rs

@@ -1,5 +1,3 @@
-use core::unimplemented;
-
 use libregister::{RegisterR, RegisterRW};
 use super::slcr;
 pub use slcr::ArmPllSource;
@@ -103,8 +101,6 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
         };
         pll / u32::from(uart_clk_ctrl.divisor())
     }
@@ -119,8 +115,6 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::Emio =>
-                unimplemented!(),
         };
         pll / u32::from(sdio_clk_ctrl.divisor())
     }

libboard_zynq/src/clocks/source.rs

@@ -6,8 +6,6 @@ use super::slcr;
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_coraz7")]
 pub const PS_CLK: u32 = 50_000_000;
-#[cfg(feature = "target_ebaz4205")]
-pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_redpitaya")]
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_kasli_soc")]

libboard_zynq/src/ddr/mod.rs

@@ -16,10 +16,6 @@ const DDR_FREQ: u32 = 666_666_666;
 /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
 const DDR_FREQ: u32 = 525_000_000;
 
-#[cfg(feature = "target_ebaz4205")]
-/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
-const DDR_FREQ: u32 = 533_333_333;
-
 #[cfg(feature = "target_redpitaya")]
 /// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
 const DDR_FREQ: u32 = 533_333_333;
@@ -151,23 +147,22 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let data1_config = data0_config.clone();
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             let data0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::VrefDifferential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
+            let data1_config = slcr::DdriobConfig::zeroed()
-                feature = "target_ebaz4205",
+                .pullup_en(true);
-                feature = "target_redpitaya",
+            #[cfg(feature = "target_redpitaya")]
-                feature = "target_kasli_soc",
+            let data0_config = slcr::DdriobConfig::zeroed()
-            ))]
+                .inp_type(slcr::DdriobInputType::VrefDifferential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
             let data1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             slcr.ddriob_data0.write(data0_config);
@@ -181,23 +176,22 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let diff1_config = diff0_config.clone();
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             let diff0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::Differential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
+            let diff1_config = slcr::DdriobConfig::zeroed()
-                feature = "target_ebaz4205",
+                .pullup_en(true);
-                feature = "target_redpitaya",
+            #[cfg(feature = "target_redpitaya")]
-                feature = "target_kasli_soc",
+            let diff0_config = slcr::DdriobConfig::zeroed()
-            ))]
+                .inp_type(slcr::DdriobInputType::Differential)
+                .term_en(true)
+                .dci_type(slcr::DdriobDciType::Termination)
+                .output_en(slcr::DdriobOutputEn::Obuf);
+            #[cfg(feature = "target_redpitaya")]
             let diff1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             slcr.ddriob_diff0.write(diff0_config);
@@ -216,12 +210,7 @@ impl DdrRam {
                 slcr.ddriob_drive_slew_clock.write(0x00F9861C);
             }
 
-            #[cfg(any(
+            #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-                feature = "target_coraz7",
-                feature = "target_ebaz4205",
-                feature = "target_redpitaya",
-                feature = "target_kasli_soc",
-            ))]
             slcr.ddriob_ddr_ctrl.modify(|_, w| w
                     .vref_int_en(false)
                     .vref_ext_en_lower(true)
@@ -235,6 +224,13 @@ impl DdrRam {
                     .vref_ext_en_lower(false)
                     .vref_ext_en_upper(false)
             );
+            #[cfg(feature = "target_redpitaya")]
+            slcr.ddriob_ddr_ctrl.modify(|_, w| w
+                    .vref_int_en(false)
+                    .vref_ext_en_lower(true)
+                    .vref_ext_en_upper(false)
+                    .refio_en(true)
+            );
         });
     }
 
@@ -246,13 +242,6 @@ impl DdrRam {
                 .t_rfc_min(0x9e)
                 .post_selfref_gap_x32(0x10)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param0.write(
-            regs::DramParam0::zeroed()
-                .t_rc(0x1a)
-                .t_rfc_min(0x56)
-                .post_selfref_gap_x32(0x10)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param0.write(
             regs::DramParam0::zeroed()
@@ -267,12 +256,6 @@ impl DdrRam {
                 .t_rfc_min(0x56)
                 .post_selfref_gap_x32(0x10)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param1.modify(
-            |_, w| w
-                .t_faw(0x16)
-                .t_ras_min(0x13)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param1.modify(
             |_, w| w
@@ -294,11 +277,6 @@ impl DdrRam {
                 .rd2pre(0x4)
                 .t_rcd(0x7)
         );
-        #[cfg(feature = "target_ebaz4205")]
-        self.regs.dram_param3.modify(
-            |_, w| w
-                .t_rp(7)
-        );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param3.modify(
             |_, w| w
@@ -320,21 +298,19 @@ impl DdrRam {
                 .emr(0x4)
         );
 
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
         self.regs.phy_configs[2].modify(
             |_, w| w.data_slice_in_use(false)
         );
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
+        self.regs.phy_configs[3].modify(
-            feature = "target_ebaz4205",
+            |_, w| w.data_slice_in_use(false)
-            feature = "target_redpitaya",
+        );
-            feature = "target_kasli_soc",
+        #[cfg(feature = "target_redpitaya")]
-        ))]
+        self.regs.phy_configs[2].modify(
+            |_, w| w.data_slice_in_use(false)
+        );
+        #[cfg(feature = "target_redpitaya")]
         self.regs.phy_configs[3].modify(
             |_, w| w.data_slice_in_use(false)
         );
@@ -378,11 +354,7 @@ impl DdrRam {
                 .gatelvl_init_ratio(0xee)
         );
 
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
-            feature = "target_ebaz4205",
-            feature = "target_kasli_soc"),
-        )]
         self.regs.reg_64.modify(
             |_, w| w
                 .phy_ctrl_slave_ratio(0x100)
@@ -418,12 +390,9 @@ impl DdrRam {
     fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
         #[cfg(feature = "target_zc706")]
         let width = regs::DataBusWidth::Width32bit;
-        #[cfg(any(
+        #[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
-            feature = "target_coraz7",
+        let width = regs::DataBusWidth::Width16bit;
-            feature = "target_ebaz4205",
+        #[cfg(feature = "target_redpitaya")]
-            feature = "target_redpitaya",
-            feature = "target_kasli_soc",
-        ))]
         let width = regs::DataBusWidth::Width16bit;
         self.regs.ddrc_ctrl.modify(|_, w| w
             .soft_rstb(false)
@@ -441,7 +410,6 @@ impl DdrRam {
         }
         #[cfg(any(
             feature = "target_coraz7",
-            feature = "target_ebaz4205",
             feature = "target_redpitaya",
             feature = "target_kasli_soc",
         ))]
@@ -482,8 +450,6 @@ impl DdrRam {
             feature = "target_kasli_soc",
         ))]
         let megabytes = 512;
-        #[cfg(feature = "target_ebaz4205")]
-        let megabytes = 256;
 
         megabytes * 1024 * 1024
     }

libboard_zynq/src/error_led.rs

@@ -1,114 +0,0 @@
-use libregister::{RegisterRW, RegisterW};
-use libregister::{register, register_at, register_bit, register_bits};
-use super::slcr;
-
-pub struct ErrorLED {
-    regs: RegisterBlock,
-}
-
-impl ErrorLED {
-    #[cfg(feature = "target_kasli_soc")]
-    pub fn error_led() -> Self {
-        slcr::RegisterBlock::unlocked(|slcr| {
-            // Error LED at MIO pin 37
-            slcr.mio_pin_37.write(
-                slcr::MioPin37::zeroed()
-                    .l3_sel(0b000)
-                    .io_type(slcr::IoBufferType::Lvcmos25)
-                    .pullup(true)
-                    .disable_rcvr(true)
-            );
-        });
-
-        Self::error_led_common(0xFFFF - 0x0080)
-    }
-
-    fn error_led_common(gpio_output_mask: u16) -> Self {
-        // Setup register block
-        let self_ = Self {
-            regs: RegisterBlock::error_led(),
-        };
-
-        // Setup GPIO output mask
-        self_.regs.gpio_output_mask.modify(|_, w| {
-            w.mask(gpio_output_mask)
-        });
-
-        self_.regs.gpio_direction.modify(|_, w| {
-            w.lederr(true)
-        });
-
-        self_
-    }
-
-    fn led_oe(&mut self, oe: bool) {
-        self.regs.gpio_output_enable.modify(|_, w| {
-             w.lederr(oe)
-        })
-    }
-
-    fn led_o(&mut self, o: bool) {
-        self.regs.gpio_output_mask.modify(|_, w| {
-             w.lederr_o(o)
-        })
-    }
-
-    pub fn toggle(&mut self, state: bool) {
-        self.led_o(state);
-        self.led_oe(state);
-    }
-}
-
-
-pub struct RegisterBlock {
-    pub gpio_output_mask: &'static mut GPIOOutputMask,
-    pub gpio_direction: &'static mut GPIODirection,
-    pub gpio_output_enable: &'static mut GPIOOutputEnable,
-}
-
-impl RegisterBlock {
-    pub fn error_led() -> Self {
-        Self {
-            gpio_output_mask: GPIOOutputMask::new(),
-            gpio_direction: GPIODirection::new(),
-            gpio_output_enable: GPIOOutputEnable::new()
-        }
-    }
-}
-
-register!(gpio_output_mask,
-            /// MASK_DATA_1_LSW:
-            /// Maskable output data for MIO[47:32]
-            GPIOOutputMask, RW, u32);
-#[cfg(feature = "target_kasli_soc")]
-register_at!(GPIOOutputMask, 0xE000A008, new);
-#[cfg(feature = "target_kasli_soc")]
-register_bit!(gpio_output_mask,
-              /// Output for LED_ERR (MIO[37])
-              lederr_o, 5);
-#[cfg(feature = "target_kasli_soc")]
-register_bits!(gpio_output_mask,
-               mask, u16, 16, 31);
-
-register!(gpio_direction,
-          /// DIRM_1:
-          /// Direction mode for MIO[53:32]; 0/1 = in/out
-          GPIODirection, RW, u32);
-#[cfg(feature = "target_kasli_soc")]
-register_at!(GPIODirection, 0xE000A244, new);
-#[cfg(feature = "target_kasli_soc")]
-register_bit!(gpio_direction,
-              /// Direction for LED_ERR
-              lederr, 5);
-
-register!(gpio_output_enable,
-          /// OEN_1:
-          /// Output enable for MIO[53:32]
-          GPIOOutputEnable, RW, u32);
-#[cfg(feature = "target_kasli_soc")]
-register_at!(GPIOOutputEnable, 0xE000A248, new);
-#[cfg(feature = "target_kasli_soc")]
-register_bit!(gpio_output_enable,
-              /// Output enable for LED_ERR
-              lederr, 5);
-              

libboard_zynq/src/eth/mod.rs

@@ -13,9 +13,6 @@ mod regs;
 pub mod rx;
 pub mod tx;
 
-use super::time::Milliseconds;
-use embedded_hal::timer::CountDown;
-
 /// Size of all the buffers
 pub const MTU: usize = 1536;
 /// Maximum MDC clock
@@ -65,31 +62,17 @@ impl Gem for Gem0 {
             slcr.gem0_clk_ctrl.write(
                 // 0x0050_0801: 8, 5: 100 Mb/s
                 // ...: 8, 1: 1000 Mb/s
-                #[cfg(not(feature = "target_ebaz4205"))]
                 slcr::GemClkCtrl::zeroed()
                     .clkact(true)
                     .srcsel(slcr::PllSource::IoPll)
                     .divisor(divisor0 as u8)
-                    .divisor1(divisor1 as u8),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
-                slcr::GemClkCtrl::zeroed()
-                    .clkact(true)
-                    .srcsel(slcr::PllSource::Emio)
-                    .divisor(divisor0 as u8)
                     .divisor1(divisor1 as u8)
             );
             // Enable gem0 recv clock
             slcr.gem0_rclk_ctrl.write(
                 // 0x0000_0801
-                #[cfg(not(feature = "target_ebaz4205"))]
-                slcr::RclkCtrl::zeroed()
-                    .clkact(true),
-                // ebaz4205 -- EMIO
-                #[cfg(feature = "target_ebaz4205")]
                 slcr::RclkCtrl::zeroed()
                     .clkact(true)
-                    .srcsel(true)
             );
         });
     }
@@ -168,7 +151,6 @@ pub struct Eth<GEM: Gem, RX, TX> {
 
 impl Eth<Gem0, (), ()> {
     pub fn eth0(macaddr: [u8; 6]) -> Self {
-        #[cfg(not(feature = "target_ebaz4205"))]
         slcr::RegisterBlock::unlocked(|slcr| {
             // Manual example: 0x0000_1280
             // MDIO
@@ -318,18 +300,11 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
     fn gem_common(macaddr: [u8; 6]) -> Self {
         GEM::setup_clock(TX_1000);
 
-        #[cfg(feature="target_kasli_soc")]
-        {
-            let mut eth_reset_pin = PhyRst::rst_pin();
-            eth_reset_pin.reset();
-        }
-
         let mut inner = EthInner {
             gem: PhantomData,
             link: None,
         };
         inner.init();
-
         inner.configure(macaddr);
 
         let phy = Phy::find(&mut inner).expect("phy");
@@ -507,69 +482,6 @@ impl<'a, GEM: Gem> smoltcp::phy::Device<'a> for &mut Eth<GEM, rx::DescList, tx::
     }
 }
 
-pub struct PhyRst {
-    regs: regs::GpioRegisterBlock,
-    count_down: super::timer::global::CountDown<Milliseconds>,
-}
-
-impl PhyRst {
-    pub fn rst_pin() -> Self {
-        slcr::RegisterBlock::unlocked(|slcr| {
-            // Hardware Reset for PHY
-            slcr.mio_pin_47.write(
-                slcr::MioPin47::zeroed()
-                    .l3_sel(0b000)
-                    .io_type(slcr::IoBufferType::Lvcmos18)
-                    .pullup(true)
-                    .disable_rcvr(true)
-            );
-        });
-        Self::eth_reset_common(0xFFFF - 0x8000)
-    }
-    
-    fn delay_ms(&mut self, ms: u64) {
-        self.count_down.start(Milliseconds(ms));
-        nb::block!(self.count_down.wait()).unwrap();
-    }
-
-    fn eth_reset_common(gpio_output_mask: u16) -> Self {
-        let self_ = Self {
-            regs: regs::GpioRegisterBlock::regs(),
-            count_down: unsafe { super::timer::GlobalTimer::get() }.countdown(),
-        };
-
-        // Setup GPIO output mask
-        self_.regs.gpio_output_mask.modify(|_, w| {
-            w.mask(gpio_output_mask)
-        });
-
-        self_.regs.gpio_direction.modify(|_, w| {
-            w.phy_rst(true)
-        });
-        
-        self_
-    }
-
-    fn oe(&mut self, oe: bool) {
-        self.regs.gpio_output_enable.modify(|_, w| {
-            w.phy_rst(oe)
-        })
-    }
-
-    fn toggle(&mut self, o: bool) {
-        self.regs.gpio_output_mask.modify(|_, w| {
-            w.phy_rst(o)
-        })
-    }
-
-    pub fn reset(&mut self) {
-        self.toggle(false); // drive phy_rst (active LOW) pin low
-        self.oe(true);         // enable pin's output
-        self.delay_ms(10);
-        self.toggle(true);
-    }
-}
-
 
 struct EthInner<GEM: Gem> {
     gem: PhantomData<GEM>,

libboard_zynq/src/eth/phy/mod.rs

@@ -83,7 +83,6 @@ pub struct Phy {
 const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
-const OUI_ICPLUS : u32 = 0x0090c3;
 
 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]
@@ -118,12 +117,6 @@ impl Phy {
                     model: 0,
                     ..
                 }) => true,
-                Some(PhyIdentifier {
-                    oui: OUI_ICPLUS,
-                    // IP101G-DS-R01
-                    model: 5,
-                    rev: 4,
-                }) => true,
                 _ => false,
             }
         }).map(|addr| Phy { addr })

libboard_zynq/src/eth/phy/status.rs

@@ -55,27 +55,7 @@ impl Status {
     pub fn get_link(&self) -> Option<Link> {
         if ! self.link_status() {
             None
-        } else if self.cap_100base_tx_full() {
+        } else if self.cap_10base_t_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_100base_tx_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_100base_t4() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_10base_t2_full() {
-            Some(Link {
-                speed: LinkSpeed::S10,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_10base_t2_half() {
             Some(Link {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Half,
@@ -85,11 +65,31 @@ impl Status {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Full,
             })
-        } else if self.cap_10base_t_half() {
+        } else if self.cap_10base_t2_half() {
             Some(Link {
                 speed: LinkSpeed::S10,
                 duplex: LinkDuplex::Half,
             })
+        } else if self.cap_10base_t2_full() {
+            Some(Link {
+                speed: LinkSpeed::S10,
+                duplex: LinkDuplex::Full,
+            })
+        } else if self.cap_100base_t4() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_half() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_full() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Full,
+            })
         } else {
             None
         }

libboard_zynq/src/eth/regs.rs

@@ -110,49 +110,6 @@ pub struct RegisterBlock {
     pub design_cfg5: RO<u32>,
 }
 
-pub struct GpioRegisterBlock {
-    pub gpio_output_mask: &'static mut OutputMask,
-    pub gpio_direction: &'static mut Direction,
-    pub gpio_output_enable: &'static mut OutputEnable,
-}
-
-impl GpioRegisterBlock {
-    pub fn regs() -> Self {
-        Self {
-            gpio_output_mask: OutputMask::new(),
-            gpio_direction: Direction::new(),
-            gpio_output_enable: OutputEnable::new(),
-        }
-    }
-}
-
-register!(gpio_output_mask, 
-            /// MASK_DATA_1_SW:
-            /// Maskable output data for MIO[47:32]
-            OutputMask, RW, u32);
-register_at!(OutputMask, 0xE000A008, new);
-register_bit!(gpio_output_mask, 
-            /// Output for PHY_RST (MIO[47])
-            phy_rst, 15);
-register_bits!(gpio_output_mask,
-            mask, u16, 16, 31);
-register!(gpio_direction, 
-            /// DIRM_1:
-            /// Direction mode for MIO[53:32]; 0/1 = in/out
-            Direction, RW, u32);
-register_at!(Direction, 0xE000A244, new);
-register_bit!(gpio_direction,
-            /// Direction for PHY_RST
-            phy_rst, 15);
-register!(gpio_output_enable,
-            /// OEN_1:
-            /// Output enable for MIO[53:32]
-            OutputEnable, RW, u32);
-register_at!(OutputEnable, 0xE000A248, new);
-register_bit!(gpio_output_enable,
-            /// Output enable for PHY_RST
-            phy_rst, 15);
-    
 register_at!(RegisterBlock, 0xE000B000, gem0);
 register_at!(RegisterBlock, 0xE000C000, gem1);
 

libboard_zynq/src/gic.rs

@@ -115,7 +115,7 @@ impl InterruptController {
         let m = (id.0 >> 2) as usize;
         let n = (8 * (id.0 & 3)) as usize;
         unsafe {
-            self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
+            self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1));
         }
 
         // sensitivity

libboard_zynq/src/i2c/eeprom.rs

@@ -4,7 +4,6 @@ use embedded_hal::timer::CountDown;
 
 pub struct EEPROM<'a> {
     i2c: &'a mut I2c,
-    #[cfg(not(feature = "target_ebaz4205"))]
     port: u8,
     address: u8,
     page_size: u8,
@@ -47,11 +46,6 @@ impl<'a> EEPROM<'a> {
         Ok(())
     }
 
-    #[cfg(feature = "target_ebaz4205")]
-    fn select(&mut self) -> Result<(), &'static str> {
-        Ok(())
-    }
-
     /// Random read
     pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
         self.select()?;

libboard_zynq/src/i2c/mod.rs

@@ -2,13 +2,10 @@
 
 mod regs;
 pub mod eeprom;
-#[cfg(not(feature = "target_ebaz4205"))]
 use super::slcr;
 use super::time::Microseconds;
 use embedded_hal::timer::CountDown;
-use libregister::{RegisterR, RegisterRW};
+use libregister::{RegisterR, RegisterRW, RegisterW};
-#[cfg(not(feature = "target_ebaz4205"))]
-use libregister::RegisterW;
 #[cfg(feature = "target_kasli_soc")]
 use log::info;
 
@@ -25,10 +22,9 @@ pub struct I2c {
 }
 
 impl I2c {
-    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
     pub fn i2c0() -> Self {
         // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
-        #[cfg(not(feature = "target_ebaz4205"))]
         slcr::RegisterBlock::unlocked(|slcr| {
             // SCL
             slcr.mio_pin_50.write(
@@ -57,6 +53,8 @@ impl I2c {
                     .pullup(false)
                     .disable_rcvr(true)
             );
+            // Reset
+            slcr.gpio_rst_ctrl.reset_gpio();
         });
 
         Self::i2c_common(0xFFFF - 0x000C, 0xFFFF - 0x0002)

libboard_zynq/src/i2c/regs.rs

@@ -21,7 +21,6 @@ use libregister::{
 // Current compatibility:
 // zc706: GPIO 50, 51 == SCL, SDA
 // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
-// ebaz4205: GPIO (EMIO)
 
 pub struct RegisterBlock {
     pub gpio_output_mask: &'static mut GPIOOutputMask,
@@ -49,17 +48,17 @@ register!(gpio_output_mask,
           /// MASK_DATA_1_MSW:
           /// Maskable output data for MIO[53:48]
           GPIOOutputMask, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputMask, 0xE000A00C, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
               /// Output for SCL
               scl_o, 2);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
               /// Output for SDA
               sda_o, 3);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bits!(gpio_output_mask,
                /// Mask for keeping bits except SCL and SDA unchanged
                mask, u16, 16, 31);
@@ -83,13 +82,13 @@ register!(gpio_input,
           /// DATA_1_RO:
           /// Input data for MIO[53:32]
           GPIOInput, RO, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOInput, 0xE000A064, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
               /// Input for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
               /// Input for SDA
               sda, 19);
@@ -99,13 +98,13 @@ register!(gpio_direction,
           /// DIRM_1:
           /// Direction mode for MIO[53:32]; 0/1 = in/out
           GPIODirection, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIODirection, 0xE000A244, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
               /// Direction for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
               /// Direction for SDA
               sda, 19);
@@ -118,13 +117,13 @@ register!(gpio_output_enable,
           /// OEN_1:
           /// Output enable for MIO[53:32]
           GPIOOutputEnable, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputEnable, 0xE000A248, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
               /// Output enable for SCL
               scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
               /// Output enable for SDA
               sda, 19);

libboard_zynq/src/lib.rs

@@ -19,9 +19,7 @@ pub mod gic;
 pub mod time;
 pub mod timer;
 pub mod sdio;
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 pub mod i2c;
 pub mod logger;
 pub mod ps7_init;
-#[cfg(feature="target_kasli_soc")]
-pub mod error_led;

libboard_zynq/src/sdio/mod.rs

@@ -116,8 +116,8 @@ impl Sdio {
                         .speed(true),
                 );
             }
-            // kasli_soc and redpitaya card detect pin
+            // redpitaya card detect pin
-            #[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
+            #[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
             {
                 unsafe {
                     slcr.sd0_wp_cd_sel.write(46 << 16);
@@ -128,20 +128,6 @@ impl Sdio {
                         .speed(true),
                 );
             }
-            // ebaz4205 card detect pin
-            #[cfg(feature = "target_ebaz4205")]
-            {
-                unsafe {
-                    slcr.sd0_wp_cd_sel.write(34 << 16);
-                }
-                slcr.mio_pin_34.write(
-                    slcr::MioPin34::zeroed()
-                        .io_type(slcr::IoBufferType::Lvcmos33)
-                        .pullup(true)
-                        .speed(true),
-                );
-            }
-
             slcr.sdio_rst_ctrl.reset_sdio0();
             slcr.aper_clk_ctrl.enable_sdio0();
             slcr.sdio_clk_ctrl.enable_sdio0();

libboard_zynq/src/slcr.rs

@@ -9,11 +9,9 @@ use libregister::{
 
 #[repr(u8)]
 pub enum PllSource {
-    IoPll  = 0b000,
+    IoPll  = 0b00,
-    ArmPll = 0b010,
+    ArmPll = 0b10,
-    DdrPll = 0b011,
+    DdrPll = 0b11,
-    // Ethernet controller 0 EMIO clock
-    Emio   = 0b100,
 }
 
 #[repr(u8)]
@@ -589,17 +587,6 @@ register_bit!(a9_cpu_rst_ctrl, a9_clkstop0, 4);
 register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
 register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
 
-pub fn reboot() {
-    RegisterBlock::unlocked(|slcr| {
-        unsafe {
-            let reboot = slcr.reboot_status.read();
-            slcr.reboot_status.write(reboot & 0xF0FFFFFF);
-            slcr.pss_rst_ctrl.modify(|_, w| w.soft_rst(true));
-        }
-    });
-}
-
-
 #[derive(Clone, Copy, Debug, PartialEq)]
 #[repr(u8)]
 pub enum BootModePins {
@@ -618,7 +605,7 @@ register_bit!(boot_mode, jtag_routing, 3);
 register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 2);
 
 register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
-register_bit!(pss_rst_ctrl, soft_rst, 0);
+register_bit!(pss_rst_ctrl, soft_rst, 1);
 
 /// Used for MioPin*.io_type
 #[repr(u8)]

libboard_zynq/src/stdio.rs

@@ -47,11 +47,7 @@ impl DerefMut for LazyUart {
             LazyUart::Uninitialized => {
                 #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
                 let uart = Uart::uart0(UART_RATE);
-                #[cfg(any(
+                #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
-                    feature = "target_zc706",
-                    feature = "target_ebaz4205",
-                    feature = "target_kasli_soc",
-                ))]
                 let uart = Uart::uart1(UART_RATE);
                 *self = LazyUart::Initialized(uart);
                 self

libboard_zynq/src/uart/mod.rs

@@ -79,39 +79,6 @@ impl Uart {
         self_
     }
 
-    #[cfg(feature = "target_ebaz4205")]
-    pub fn uart1(baudrate: u32) -> Self {
-        slcr::RegisterBlock::unlocked(|slcr| {
-            // Route UART 1 RxD/TxD Signals to MIO Pins
-            // TX pin
-            slcr.mio_pin_24.write(
-                slcr::MioPin24::zeroed()
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-            // RX pin
-            slcr.mio_pin_25.write(
-                slcr::MioPin25::zeroed()
-                    .tri_enable(true)
-                    .l3_sel(0b111)
-                    .io_type(slcr::IoBufferType::Lvcmos33)
-                    .pullup(true)
-            );
-        });
-
-        slcr::RegisterBlock::unlocked(|slcr| {
-            slcr.uart_rst_ctrl.reset_uart1();
-            slcr.aper_clk_ctrl.enable_uart1();
-            slcr.uart_clk_ctrl.enable_uart1();
-        });
-        let mut self_ = Uart {
-            regs: regs::RegisterBlock::uart1(),
-        };
-        self_.configure(baudrate);
-        self_
-    }
-
     pub fn write_byte(&mut self, value: u8) {
         while self.tx_fifo_full() {}
 

libconfig/Cargo.toml

@@ -6,24 +6,14 @@ edition = "2018"
 
 [dependencies]
 libboard_zynq = { path = "../libboard_zynq" }
+core_io = { version = "0.1", features = ["collections"] }
+fatfs = { version = "0.3", features = ["core_io"], default-features = false }
 log = "0.4"
 
-[dependencies.core_io]
-git = "https://git.m-labs.hk/M-Labs/rs-core_io.git"
-rev = "e9d3edf027"
-features = ["collections"]
-
-[dependencies.fatfs]
-git = "https://git.m-labs.hk/M-Labs/rust-fatfs.git"
-rev = "4b5e420084"
-default-features = false
-features = ["core_io"]
-
 [features]
 target_zc706 = []
 target_coraz7 = []
-target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = []
-fat_lfn = [ "fatfs/alloc" ]
+fat_lfn = [ "fatfs/alloc" ]

libconfig/src/net_settings.rs

@@ -59,10 +59,6 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
     let mut hardware_addr = get_address_from_eeprom();
     #[cfg(feature = "target_kasli_soc")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x57]);
-    #[cfg(feature = "target_ebaz4205")]
-    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 57);
 
     if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
         hardware_addr = addr;

libcortex_a9/src/asm.rs

@@ -1,60 +1,53 @@
-use core::arch::asm;
-
 /// The classic no-op
 #[inline]
 pub fn nop() {
-    unsafe { asm!("nop") }
+    unsafe { llvm_asm!("nop" :::: "volatile") }
 }
 
 /// Wait For Event
 #[inline]
 pub fn wfe() {
-    unsafe { asm!("wfe") }
+    unsafe { llvm_asm!("wfe" :::: "volatile") }
 }
 
 /// Send Event
 #[inline]
 pub fn sev() {
-    unsafe { asm!("sev") }
+    unsafe { llvm_asm!("sev" :::: "volatile") }
 }
 
 /// Data Memory Barrier
 #[inline]
 pub fn dmb() {
-    unsafe { asm!("dmb") }
+    unsafe { llvm_asm!("dmb" :::: "volatile") }
 }
 
 /// Data Synchronization Barrier
 #[inline]
 pub fn dsb() {
-    unsafe { asm!("dsb") }
+    unsafe { llvm_asm!("dsb" :::: "volatile") }
 }
 
 /// Instruction Synchronization Barrier
 #[inline]
 pub fn isb() {
-    unsafe { asm!("isb") }
+    unsafe { llvm_asm!("isb" :::: "volatile") }
-}
-
-/// Enable FIQ
-#[inline]
-pub unsafe fn enable_fiq() {
-    asm!("cpsie f");
 }
 
 /// Enable IRQ
 #[inline]
 pub unsafe fn enable_irq() {
-    asm!("cpsie i");
+    llvm_asm!("cpsie i":::: "volatile");
 }
 
 /// Disable IRQ, return if IRQ was originally enabled.
 #[inline]
 pub unsafe fn enter_critical() -> bool {
     let mut cpsr: u32;
-    asm!(
+    llvm_asm!(
-        "mrs {}, cpsr
+        "mrs $0, cpsr
-         cpsid i", lateout(reg) cpsr);
+         cpsid i"
+         : "=r"(cpsr) ::: "volatile");
     (cpsr & (1 << 7)) == 0
 }
 
@@ -66,18 +59,18 @@ pub unsafe fn exit_critical(enable: bool) {
     } else {
         0
     };
-    asm!(
+    llvm_asm!(
         "mrs r1, cpsr
-         bic r1, r1, {}
+         bic r1, r1, $0
          msr cpsr_c, r1"
-         , in(reg) mask, out("r1") _);
+         :: "r"(mask) : "r1");
 }
 
 /// Exiting IRQ
 #[inline]
 pub unsafe fn exit_irq() {
-    asm!("
+    llvm_asm!("
         mrs r0, SPSR
         msr CPSR, r0
-        ", out("r0") _);
+        " ::: "r0");
 }

libcortex_a9/src/cache.rs

@@ -1,12 +1,11 @@
 use super::asm::{dmb, dsb};
 use super::l2c::*;
-use core::arch::asm;
 
 /// Invalidate TLBs
 #[inline(always)]
 pub fn tlbiall() {
     unsafe {
-        asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0);
+        llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -14,7 +13,7 @@ pub fn tlbiall() {
 #[inline(always)]
 pub fn iciallu() {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0);
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -22,7 +21,7 @@ pub fn iciallu() {
 #[inline(always)]
 pub fn bpiall() {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0);
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
     }
 }
 
@@ -30,7 +29,7 @@ pub fn bpiall() {
 #[inline(always)]
 pub fn dccsw(setway: u32) {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway);
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -42,7 +41,7 @@ pub fn dcisw(setway: u32) {
         // also see example code (for DCCISW, but DCISW will be
         // analogous) "Example code for cache maintenance operations"
         // on pages B2-1286 and B2-1287.
-        asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway);
+        llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -50,7 +49,7 @@ pub fn dcisw(setway: u32) {
 #[inline(always)]
 pub fn dccisw(setway: u32) {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway);
+        llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -70,7 +69,7 @@ pub fn dciall_l1() {
 
     // select L1 data cache
     unsafe {
-        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
+        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -105,7 +104,7 @@ pub fn dcciall_l1() {
 
     // select L1 data cache
     unsafe {
-        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
+        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -157,7 +156,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
 #[inline(always)]
 pub fn dccimvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr);
+        llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
     }
 }
 
@@ -199,9 +198,10 @@ pub fn dcci_slice<T>(slice: &[T]) {
 #[inline(always)]
 pub fn dccmvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr);
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
     }
 }
+
 /// Data cache clean for an object.
 pub fn dcc<T>(object: &T) {
     dmb();
@@ -239,7 +239,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
 /// affecting more data than intended.
 #[inline(always)]
 pub unsafe fn dcimvac(addr: usize) {
-    asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr);
+    llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
 }
 
 /// Data cache clean and invalidate for an object.

libcortex_a9/src/fpu.rs

@@ -1,8 +1,7 @@
-use core::arch::asm;
 /// Enable FPU in the current core.
 pub fn enable_fpu() {
     unsafe {
-        asm!("
+        llvm_asm!("
             mrc p15, 0, r1, c1, c0, 2
             orr r1, r1, (0b1111<<20)
             mcr p15, 0, r1, c1, c0, 2
@@ -10,6 +9,6 @@ pub fn enable_fpu() {
             vmrs r1, fpexc
             orr r1, r1, (1<<30)
             vmsr fpexc, r1
-            ", out("r1") _);
+            ":::"r1");
     }
 }

libcortex_a9/src/lib.rs

@@ -1,10 +1,7 @@
 #![no_std]
+#![feature(llvm_asm, global_asm)]
 #![feature(never_type)]
-#![feature(global_asm)]
+#![feature(const_fn)]
-#![feature(asm)]
-#![allow(incomplete_features)]
-#![feature(inline_const)]
-#![feature(const_fn_trait_bound)]
 
 extern crate alloc;
 
@@ -20,7 +17,6 @@ pub mod sync_channel;
 mod uncached;
 pub use fpu::enable_fpu;
 pub use uncached::UncachedSlice;
-use core::arch::global_asm;
 
 global_asm!(include_str!("exceptions.s"));
 
@@ -40,9 +36,7 @@ pub fn notify_spin_lock() {
 }
 
 #[macro_export]
-/// Interrupt handler, which setup the stack and preserve registers before jumping to actual interrupt handler.
+/// Interrupt handler, which setup the stack and jump to actual interrupt handler.
-/// Registers r0-r12, PC, SP and CPSR are restored after the actual handler.
-/// 
 /// - `name` is the name of the interrupt, should be the same as the one defined in vector table.
 /// - `name2` is the name for the actual handler, should be different from name.
 /// - `stack0` is the stack for the interrupt handler when called from core0.
@@ -50,7 +44,8 @@ pub fn notify_spin_lock() {
 /// - `body` is the body of the actual interrupt handler, should be a normal unsafe rust function
 /// body.
 ///
-/// Note that the interrupt handler would use the same stack as normal programs by default.
+/// Note that the interrupt handler would use the same stack as normal programs by default, so
+/// interrupt handlers should not return to normal program or it may corrupt the stack.
 macro_rules! interrupt_handler {
     ($name:ident, $name2:ident, $stack0:ident, $stack1:ident, $body:block) => {
         #[link_section = ".text.boot"]
@@ -59,27 +54,19 @@ macro_rules! interrupt_handler {
         pub unsafe extern "C" fn $name() -> ! {
             asm!(
                 // setup SP, depending on CPU 0 or 1
-                // and preserve registers
-                "sub lr, lr, #4",
-                "stmfd sp!, {{r0-r12, lr}}",
                 "mrc p15, #0, r0, c0, c0, #5",
                 concat!("movw r1, :lower16:", stringify!($stack0)),
                 concat!("movt r1, :upper16:", stringify!($stack0)),
                 "tst r0, #3",
                 concat!("movwne r1, :lower16:", stringify!($stack1)),
                 concat!("movtne r1, :upper16:", stringify!($stack1)),
-                "mov r0, sp",
                 "mov sp, r1",
-                "push {{r0, r1}}",                                      // 2 registers are pushed to maintain 8 byte stack alignment 
                 concat!("bl ", stringify!($name2)),
-                "pop {{r0, r1}}",
-                "mov sp, r0",
-                "ldmfd sp!, {{r0-r12, pc}}^",                           // caret ^ : copy SPSR to the CPSR  
                 options(noreturn)
             );
         }
 
         #[no_mangle]
-        pub unsafe extern "C" fn $name2() $body
+        pub unsafe extern "C" fn $name2() -> ! $body
     };
 }

libcortex_a9/src/regs.rs

@@ -2,7 +2,6 @@ use libregister::{
     register_bit, register_bits,
     RegisterR, RegisterW, RegisterRW,
 };
-use core::arch::asm;
 
 macro_rules! def_reg_r {
     ($name:tt, $type: ty, $asm_instr:tt) => {
@@ -12,7 +11,7 @@ macro_rules! def_reg_r {
             #[inline]
             fn read(&self) -> Self::R {
                 let mut value: u32;
-                unsafe { asm!($asm_instr, lateout(reg) value) }
+                unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
                 value.into()
             }
         }
@@ -27,7 +26,7 @@ macro_rules! def_reg_w {
             #[inline]
             fn write(&mut self, value: Self::W) {
                 let value: u32 = value.into();
-                unsafe { asm!($asm_instr, in(reg) value) }
+                unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
             }
 
             #[inline]
@@ -72,29 +71,29 @@ macro_rules! wrap_reg {
 
 /// Stack Pointer
 pub struct SP;
-def_reg_r!(SP, u32, "mov {}, sp");
+def_reg_r!(SP, u32, "mov $0, sp");
-def_reg_w!(SP, u32, "mov sp, {}");
+def_reg_w!(SP, u32, "mov sp, $0");
 
 /// Link register (function call return address)
 pub struct LR;
-def_reg_r!(LR, u32, "mov {}, lr");
+def_reg_r!(LR, u32, "mov $0, lr");
-def_reg_w!(LR, u32, "mov lr, {}");
+def_reg_w!(LR, u32, "mov lr, $0");
 
 pub struct VBAR;
-def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
+def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
-def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");
+def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
 
 pub struct MVBAR;
-def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
+def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
-def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");
+def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
 
 pub struct HVBAR;
-def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
+def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
-def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");
+def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
 
 /// Multiprocess Affinity Register
 pub struct MPIDR;
-def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
+def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
 wrap_reg!(mpidr);
 register_bits!(mpidr,
                /// CPU core index
@@ -107,15 +106,15 @@ register_bit!(mpidr,
               u, 30);
 
 pub struct DFAR;
-def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");
+def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
 
 pub struct DFSR;
-def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");
+def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
 
 pub struct SCTLR;
 wrap_reg!(sctlr);
-def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
+def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
-def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
+def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
 register_bit!(sctlr,
               /// Enables MMU
               m, 0);
@@ -148,8 +147,8 @@ register_bit!(sctlr,
 /// Auxiliary Control Register
 pub struct ACTLR;
 wrap_reg!(actlr);
-def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
+def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
-def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
+def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
 // SMP bit
 register_bit!(actlr, parity_on, 9);
 register_bit!(actlr, alloc_one_way, 8);
@@ -184,17 +183,17 @@ impl ACTLR {
 
 /// Domain Access Control Register
 pub struct DACR;
-def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
+def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
-def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");
+def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
 
 /// Translation Table Base Register 0
 pub struct TTBR0;
 /// Translation Table Base Register 1
 pub struct TTBR1;
-def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
+def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
-def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
+def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
-def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
+def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
-def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
+def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
 wrap_reg!(ttbr);
 register_bits!(ttbr, table_base, u32, 14, 31);
 register_bit!(ttbr, irgn0, 6);

libcortex_a9/src/sync_channel.rs

@@ -172,15 +172,13 @@ impl<'a, T> Iterator for Receiver<'a, T> where T: Clone {
 
 #[macro_export]
 /// Macro for initializing the sync_channel with static buffer and indexes.
+/// Note that this requires `#![feature(const_in_array_repeat_expressions)]`
 macro_rules! sync_channel {
     ($t: ty, $cap: expr) => {
         {
             use core::sync::atomic::{AtomicUsize, AtomicPtr};
             use $crate::sync_channel::{Sender, Receiver};
-            const fn new_atomic() -> AtomicPtr<$t> {
+            static LIST: [AtomicPtr<$t>; $cap + 1] = [AtomicPtr::new(core::ptr::null_mut()); $cap + 1];
-                AtomicPtr::new(core::ptr::null_mut())
-            }
-            static LIST: [AtomicPtr<$t>; $cap + 1] = [const { new_atomic() }; $cap + 1];
             static WRITE: AtomicUsize = AtomicUsize::new(0);
             static READ: AtomicUsize = AtomicUsize::new(0);
             (Sender::new(&LIST, &WRITE, &READ), Receiver::new(&LIST, &WRITE, &READ))

libsupport_zynq/Cargo.toml

@@ -8,19 +8,17 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
 panic_handler = []
 dummy_irq_handler = []
-dummy_fiq_handler = []
 alloc_core = []
 
-default = ["panic_handler", "dummy_irq_handler", "dummy_fiq_handler"]
+default = ["panic_handler", "dummy_irq_handler"]
 
 [dependencies]
 r0 = "1"
-compiler_builtins = "=0.1.49"
+compiler_builtins = "=0.1.39"
 linked_list_allocator = { version = "0.8", default-features = false, features = ["const_mut_refs"] }
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }

libsupport_zynq/src/abort.rs

@@ -1,11 +1,6 @@
-use libregister::{RegisterR, RegisterW};
+use libregister::RegisterR;
-use libcortex_a9::{regs::{DFSR, MPIDR, VBAR}, interrupt_handler};
+use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler};
-use libboard_zynq::{println, stdio}; 
+use libboard_zynq::{println, stdio};
-use core::arch::asm;
-
-pub fn set_vector_table(base_addr: u32){
-    VBAR.write(base_addr);
-}
 
 interrupt_handler!(UndefinedInstruction, undefined_instruction, __irq_stack0_start, __irq_stack1_start, {
     stdio::drop_uart();
@@ -47,7 +42,6 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
     loop {}
 });
 
-#[cfg(feature = "dummy_fiq_handler")]
 interrupt_handler!(FIQ, fiq, __irq_stack0_start, __irq_stack1_start, {
     stdio::drop_uart();
     println!("FIQ");

libsupport_zynq/src/boot.rs

@@ -1,6 +1,5 @@
 use r0::zero_bss;
 use core::ptr::write_volatile;
-use core::arch::asm;
 use libregister::{
     VolatileCell,
     RegisterR, RegisterRW,
@@ -55,7 +54,6 @@ unsafe extern "C" fn boot_core0() -> ! {
         asm::dmb();
         asm::dsb();
 
-        asm::enable_fiq();
         asm::enable_irq();
         main_core0();
         panic!("return from main");
@@ -77,7 +75,6 @@ unsafe extern "C" fn boot_core1() -> ! {
         asm::dmb();
         asm::dsb();
 
-        asm::enable_fiq();
         asm::enable_irq();
         main_core1();
         panic!("return from main_core1");

libsupport_zynq/src/lib.rs

@@ -3,14 +3,13 @@
 #![feature(alloc_error_handler)]
 #![feature(panic_info_message)]
 #![feature(naked_functions)]
-#![feature(global_asm)]
 #![feature(asm)]
 
 pub extern crate alloc;
 pub extern crate compiler_builtins;
 
 pub mod boot;
-pub mod exception_vectors;
+mod abort;
 #[cfg(feature = "panic_handler")]
 mod panic;
 pub mod ram;

libsupport_zynq/src/panic.rs

@@ -1,6 +1,4 @@
 use libboard_zynq::{print, println};
-#[cfg(feature = "target_kasli_soc")]
-use libboard_zynq::error_led::ErrorLED;
 
 #[panic_handler]
 fn panic(info: &core::panic::PanicInfo) -> ! {
@@ -15,10 +13,6 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
     } else {
         println!("");
     }
-    #[cfg(feature = "target_kasli_soc")]
+
-    {
-        let mut err_led = ErrorLED::error_led();
-        err_led.toggle(true);
-    }
     loop {}
 }

openocd/ebaz4205.cfg

@@ -1,33 +0,0 @@
-# The contents of this file are partially dependend on
-# the adapter that you have. Please modify accordingly.
-adapter driver ftdi
-ftdi vid_pid 0x0403 0x6010
-ftdi channel 0
-# Every pin set as high impedance except TCK, TDI, TDO and TMS
-ftdi layout_init 0x0088 0x008b
-
-# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
-# This choice is arbitrary. Use other GPIO pin if desired.
-ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
-
-transport select jtag
-adapter speed 10000
-
-set PL_TAPID 0x13722093
-set SMP 1
-
-source ./zynq-7000.cfg
-
-reset_config srst_only srst_open_drain
-adapter srst pulse_width 250
-adapter srst delay 400
-
-source ./common.cfg
-
-reset halt
-
-# Disable MMU
-targets $_TARGETNAME_1
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
-targets $_TARGETNAME_0
-arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]

szl/Cargo.toml

@@ -8,7 +8,6 @@ edition = "2018"
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
 target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
-target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
 target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
 default = ["target_zc706"]
@@ -16,14 +15,10 @@ default = ["target_zc706"]
 [dependencies]
 log = "0.4"
 byteorder = { version = "1.3", default-features = false }
+core_io = { version = "0.1", features = ["collections"] }
+
 libboard_zynq = { path = "../libboard_zynq" }
 libsupport_zynq = { path = "../libsupport_zynq" }
 libcortex_a9 = { path = "../libcortex_a9" }
 libregister = { path = "../libregister" }
 libconfig = { path = "../libconfig" }
-
-[dependencies.core_io]
-git = "https://git.m-labs.hk/M-Labs/rs-core_io.git"
-rev = "e9d3edf027"
-features = ["collections"]
-

szl/src/main.rs

@@ -80,15 +80,12 @@ pub fn main_core0() {
     );
     info!("Simple Zynq Loader starting...");
 
-    #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
+    #[cfg(not(feature = "target_kasli_soc"))]
     const CPU_FREQ: u32 = 800_000_000;
 
     #[cfg(feature = "target_kasli_soc")]
     const CPU_FREQ: u32 = 1_000_000_000;
 
-    #[cfg(feature = "target_ebaz4205")]
-    const CPU_FREQ: u32 = 666_666_666;
-
     ArmPll::setup(2 * CPU_FREQ);
     Clocks::set_cpu_freq(CPU_FREQ);
     IoPll::setup(1_000_000_000);