M-Labs/zynq-rs
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merge into: M-Labs:master
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M-Labs:release-8
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missiannane:feature/pynq-support
missiannane:master
missiannane:release-8
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pull from: missiannane:feature/pynq-support
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missiannane:master
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2 Commits
master ... feature/py

Author SHA1 Message Date
simy46
ad03f23f3d support pynqz2 2025-01-24 12:17:29 -05:00
simy46
df8fc1aed1 new target on pynqz2 and ps clk set to 50MHz 2025-01-24 11:56:05 -05:00
2 changed files with 3 additions and 0 deletions
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1
libboard_zynq/Cargo.toml
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@ -11,6 +11,7 @@ target_coraz7 = []
target_ebaz4205 = [] target_ebaz4205 = []
target_redpitaya = [] target_redpitaya = []
target_kasli_soc = [] target_kasli_soc = []
target_pynqz2 = []
ipv6 = [ "smoltcp/proto-ipv6" ] ipv6 = [ "smoltcp/proto-ipv6" ]
[dependencies] [dependencies]

2
libboard_zynq/src/clocks/source.rs
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@ -12,6 +12,8 @@ pub const PS_CLK: u32 = 33_333_333;
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
pub const PS_CLK: u32 = 33_333_333; pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_pynqz2")]
pub const PS_CLK: u32 = 50_000_000;
/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt)) /// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[ const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[