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No commits in common. "e9b80eaef9afc7b9ccff9274e1dcec3cfbdb99b0" and "f3676c945a4dce74cb1379dba0f1d8473e6ef5cc" have entirely different histories.
e9b80eaef9
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f3676c945a
30
src/main.rs
30
src/main.rs
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@ -29,41 +29,13 @@ mod ram;
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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pub fn main() {
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println!("\nzc706 main");
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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print!("Flash {}:", i);
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for b in &flash_ram[(i * 16 * 1024 * 1024)..][..128] {
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print!(" {:02X}", *b);
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}
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println!("");
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}
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let mut flash = flash.stop();
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println!("Main.");
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let mut ddr = zynq::ddr::DdrRam::new();
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println!("DDR: {:?}", ddr.status());
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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print!("Flash {} ID:", i);
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for b in flash_io.rdid() {
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print!(" {:02X}", b);
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}
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println!("");
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print!("Flash {} I/O:", i);
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for o in 0..4 {
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for b in flash_io.read(32 * o, 32) {
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print!(" {:02X}", b);
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}
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}
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println!("");
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flash = flash_io.stop();
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}
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let core1_stack = vec![0; 2048];
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println!("{} bytes stack for core1", core1_stack.len());
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boot::Core1::start(core1_stack);
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@ -10,7 +10,7 @@ impl<I: Iterator<Item = u32>> BytesTransferExt for I {
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fn bytes_transfer(self) -> BytesTransfer<Self> {
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BytesTransfer {
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iter: self,
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shift: 0,
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shift: 32,
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word: 0,
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}
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}
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@ -26,15 +26,15 @@ impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
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type Item = u8;
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fn next(&mut self) -> Option<u8> {
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if self.shift > 0 {
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self.shift -= 8;
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if self.shift < 24 {
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self.shift += 8;
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Some((self.word >> self.shift) as u8)
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} else {
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self.shift = 0;
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self.iter.next()
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.and_then(|word| {
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self.shift = 32;
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.map(|word| {
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self.word = word;
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self.next()
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word as u8
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})
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}
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}
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@ -233,7 +233,7 @@ impl Flash<()> {
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// Initialize RX/TX pipes thresholds
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unsafe {
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self.regs.rx_thres.write(1);
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self.regs.rx_thres.write(32);
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self.regs.tx_thres.write(1);
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}
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}
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@ -272,7 +272,6 @@ impl Flash<()> {
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self.regs.config.modify(|_, w| w
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.man_start_en(true)
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.manual_cs(true)
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.endian(true)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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@ -281,7 +280,7 @@ impl Flash<()> {
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.mode_en(true)
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// 2 devices
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.two_mem(true)
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.sep_bus(true)
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// .sep_bus(true)
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.u_page(chip_index != 0)
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// Manual I/O mode
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.lq_mode(false)
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@ -317,45 +316,41 @@ impl Flash<Manual> {
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/// Read Configuration Register
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pub fn rdcr(&mut self) -> u8 {
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let args = Some((INST_RDCR as u32) << 24);
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self.transfer(args.into_iter(), 4)
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self.transfer(INST_RDCR, core::iter::empty())
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.bytes_transfer().skip(1)
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.next().unwrap() as u8
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}
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/// Read Identifiaction
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>>>> {
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let args = Some((INST_RDID as u32) << 24);
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self.transfer(args.into_iter(), 0x44)
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::iter::Empty<u32>>>> {
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self.transfer(INST_RDID, core::iter::empty())
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.bytes_transfer().skip(1)
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}
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/// Read flash data
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pub fn read(&mut self, offset: u32, len: usize) -> core::iter::Take<core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>>>>> {
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// INST_READ
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let args = Some((0x03 << 24) | (offset as u32));
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self.transfer(args.into_iter(), len + 6)
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.bytes_transfer().skip(6).take(len)
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}
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pub fn transfer<'s: 't, 't, Args>(&'s mut self, args: Args, len: usize) -> Transfer<'t, Args>
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pub fn transfer<'s: 't, 't, Args>(&'s mut self, inst_code: u8, args: Args) -> Transfer<'t, Args>
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where
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Args: Iterator<Item = u32>,
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{
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Transfer::new(self, args, len)
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Transfer::new(self, inst_code, args)
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}
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pub fn read(&mut self, offset: u32, len: usize) -> core::iter::Take<core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>>>>> {
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// TODO:
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let args = Some(0u32);
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// Read
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self.transfer(0x03, args.into_iter())
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.bytes_transfer().skip(1).take(len)
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}
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}
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pub struct Transfer<'a, Args: Iterator<Item = u32>> {
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flash: &'a mut Flash<Manual>,
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args: Args,
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sent: usize,
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received: usize,
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len: usize,
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}
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impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self
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pub fn new(flash: &'a mut Flash<Manual>, inst_code: u8, mut args: Args) -> Self
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where
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Args: Iterator<Item = u32>,
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{
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@ -364,45 +359,37 @@ impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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regs::Enable::zeroed()
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.spi_en(true)
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);
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while flash.regs.intr_status.read().rx_fifo_not_empty() {
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flash.regs.rx_data.read();
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}
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let mut xfer = Transfer {
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unsafe {
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flash.regs.txd1.write(inst_code.into());
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}
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flash.regs.config.modify(|_, w| w.man_start_com(true));
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// Flush after `txd1` access
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while !flash.regs.intr_status.read().tx_fifo_not_full() {}
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while !flash.regs.intr_status.read().tx_fifo_full() {
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let arg = args.next().unwrap_or(0);
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unsafe {
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flash.regs.txd0.write(arg);
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}
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}
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flash.regs.config.modify(|_, w| w.man_start_com(true));
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Transfer {
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flash,
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args,
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sent: 0,
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received: 0,
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len,
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};
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xfer.fill_tx_fifo();
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xfer.flash.regs.config.modify(|_, w| w.man_start_com(true));
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xfer
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}
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fn fill_tx_fifo(&mut self) {
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while self.sent < self.len && !self.flash.regs.intr_status.read().tx_fifo_full() {
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let arg = self.args.next().unwrap_or(0);
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unsafe {
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self.flash.regs.txd0.write(arg);
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}
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self.sent += 4;
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}
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}
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fn can_read(&mut self) -> bool {
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self.flash.regs.intr_status.read().rx_fifo_not_empty()
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}
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fn read(&mut self) -> u32 {
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let rx = self.flash.regs.rx_data.read();
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self.received += 4;
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rx
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}
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}
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impl<'a, Args: Iterator<Item = u32>> Drop for Transfer<'a, Args> {
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fn drop(&mut self) {
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// Discard remaining rx_data
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while self.can_read() {
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self.read();
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while self.flash.regs.intr_status.read().rx_fifo_not_empty() {
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self.flash.regs.rx_data.read();
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}
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// Stop
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@ -421,13 +408,14 @@ impl<'a, Args: Iterator<Item = u32>> Iterator for Transfer<'a, Args> {
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type Item = u32;
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fn next<'s>(&'s mut self) -> Option<u32> {
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if self.received >= self.len {
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return None;
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while !self.flash.regs.intr_status.read().rx_fifo_not_empty() {}
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let rx = self.flash.regs.rx_data.read();
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let arg = self.args.next().unwrap_or(0);
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unsafe {
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self.flash.regs.txd0.write(arg);
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}
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self.fill_tx_fifo();
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while !self.can_read() {}
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Some(self.read())
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Some(rx)
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}
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}
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