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No commits in common. "caa69fda2e3b2c64375ecc978e0f2d73de74bc2e" and "cb1b5776cd8d30c2f7393552fce2e3f1f596c42a" have entirely different histories.
caa69fda2e
...
cb1b5776cd
13
src/abort.rs
13
src/abort.rs
|
@ -1,13 +0,0 @@
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use crate::println;
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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println!("PrefetchAbort");
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loop {}
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}
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#[no_mangle]
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pub unsafe extern "C" fn DataAbort() {
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println!("DataAbort");
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loop {}
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}
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61
src/boot.rs
61
src/boot.rs
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@ -1,61 +0,0 @@
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use r0::zero_bss;
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use crate::regs::{RegisterR, RegisterW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32;
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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match MPIDR.read() & CORE_MASK {
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0 => {
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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crate::main();
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panic!("return from main");
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});
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}
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fn l1_cache_init() {
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use crate::cortex_a9::cache::*;
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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//
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// NOTE: It is both faster and correct to only invalidate instead
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// of also flush the cache (as was done before with
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// `dccisw()`) and it is correct to perform this operation
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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}
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138
src/main.rs
138
src/main.rs
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@ -10,32 +10,98 @@
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#![allow(dead_code)]
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extern crate alloc;
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use alloc::{vec, vec::Vec};
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use core::mem::transmute;
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use alloc::{vec, vec::Vec, alloc::Layout};
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use core::alloc::GlobalAlloc;
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use core::ptr::NonNull;
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use core::cell::RefCell;
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use core::mem::{uninitialized, transmute};
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use r0::zero_bss;
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use compiler_builtins as _;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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use linked_list_allocator::Heap;
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mod boot;
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mod regs;
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mod cortex_a9;
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mod abort;
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mod panic;
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mod zynq;
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mod stdio;
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mod ram;
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mod zynq;
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use crate::regs::{RegisterR, RegisterW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32;
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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match MPIDR.read() & CORE_MASK {
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0 => {
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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main();
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panic!("return from main");
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});
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}
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fn l1_cache_init() {
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use crate::cortex_a9::cache::*;
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|
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
|
||||
// Invalidate D-Cache
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//
|
||||
// NOTE: It is both faster and correct to only invalidate instead
|
||||
// of also flush the cache (as was done before with
|
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// `dccisw()`) and it is correct to perform this operation
|
||||
// for all of the L1 data cache rather than a (previously
|
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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}
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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pub fn main() {
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fn main() {
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println!("Main.");
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let mut ddr = zynq::ddr::DdrRam::new();
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println!("DDR: {:?}", ddr.status());
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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unsafe {
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ALLOCATOR.0.borrow_mut()
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.init(ddr.ptr::<u8>() as usize, ddr.size());
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}
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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|
@ -62,7 +128,7 @@ pub fn main() {
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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let local_addr = IpAddress::v4(192, 168, 1, 28);
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let local_addr = IpAddress::v4(10, 0, 0, 1);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let mut neighbor_storage = vec![None; 256];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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|
@ -80,7 +146,7 @@ pub fn main() {
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let mut time = 0u32;
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loop {
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time += 1;
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let timestamp = Instant::from_millis(time);
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let timestamp = Instant::from_millis(time.into());
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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||||
|
@ -115,6 +181,52 @@ pub fn main() {
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// None => println!("eth tx shortage"),
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// }
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}
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}
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#[panic_handler]
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fn panic(info: &core::panic::PanicInfo) -> ! {
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println!("\nPanic: {}", info);
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zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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}
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#[global_allocator]
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static ALLOCATOR: HeapAlloc = HeapAlloc(RefCell::new(Heap::empty()));
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|
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/// LockedHeap doesn't locking properly
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struct HeapAlloc(RefCell<Heap>);
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/// FIXME: unsound; lock properly
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unsafe impl Sync for HeapAlloc {}
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unsafe impl GlobalAlloc for HeapAlloc {
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unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
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self.0.borrow_mut()
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.allocate_first_fit(layout)
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.ok()
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.map_or(0 as *mut u8, |allocation| allocation.as_ptr())
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}
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unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
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self.0.borrow_mut()
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.deallocate(NonNull::new_unchecked(ptr), layout)
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}
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}
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#[alloc_error_handler]
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fn alloc_error(_: core::alloc::Layout) -> ! {
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panic!("alloc_error")
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}
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#[no_mangle]
|
||||
pub unsafe extern "C" fn PrefetchAbort() {
|
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println!("PrefetchAbort");
|
||||
loop {}
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
pub unsafe extern "C" fn DataAbort() {
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println!("DataAbort");
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loop {}
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}
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|
|
185
src/main.rs.orig
185
src/main.rs.orig
|
@ -1,185 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
|
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#![feature(compiler_builtins_lib)]
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#![feature(never_type)]
|
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// TODO: disallow unused/dead_code when code moves into a lib crate
|
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#![allow(dead_code)]
|
||||
|
||||
use core::mem::{uninitialized, transmute};
|
||||
use r0::zero_bss;
|
||||
use compiler_builtins as _;
|
||||
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
|
||||
use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
|
||||
use smoltcp::time::Instant;
|
||||
use smoltcp::socket::SocketSet;
|
||||
|
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mod regs;
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mod cortex_a9;
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mod clocks;
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mod slcr;
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mod uart;
|
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mod stdio;
|
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mod eth;
|
||||
|
||||
use crate::regs::{RegisterR, RegisterW};
|
||||
use crate::cortex_a9::{asm, regs::*, mmu};
|
||||
|
||||
extern "C" {
|
||||
static mut __bss_start: u32;
|
||||
static mut __bss_end: u32;
|
||||
static mut __stack_start: u32;
|
||||
}
|
||||
|
||||
#[link_section = ".text.boot"]
|
||||
#[no_mangle]
|
||||
#[naked]
|
||||
pub unsafe extern "C" fn _boot_cores() -> ! {
|
||||
const CORE_MASK: u32 = 0x3;
|
||||
|
||||
match MPIDR.read() & CORE_MASK {
|
||||
0 => {
|
||||
SP.write(&mut __stack_start as *mut _ as u32);
|
||||
boot_core0();
|
||||
}
|
||||
_ => loop {
|
||||
// if not core0, infinitely wait for events
|
||||
asm::wfe();
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
#[naked]
|
||||
#[inline(never)]
|
||||
unsafe fn boot_core0() -> ! {
|
||||
l1_cache_init();
|
||||
zero_bss(&mut __bss_start, &mut __bss_end);
|
||||
|
||||
let mmu_table = mmu::L1Table::get()
|
||||
.setup_flat_layout();
|
||||
mmu::with_mmu(mmu_table, || {
|
||||
main();
|
||||
panic!("return from main");
|
||||
});
|
||||
}
|
||||
|
||||
fn l1_cache_init() {
|
||||
// Invalidate TLBs
|
||||
tlbiall();
|
||||
// Invalidate I-Cache
|
||||
iciallu();
|
||||
// Invalidate Branch Predictor Array
|
||||
bpiall();
|
||||
// Invalidate D-Cache
|
||||
dccisw();
|
||||
}
|
||||
|
||||
const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
|
||||
|
||||
fn main() {
|
||||
println!("Main.");
|
||||
let clocks = clocks::CpuClocks::get();
|
||||
println!("Clocks: {:?}", clocks);
|
||||
println!("CPU speeds: {}/{}/{}/{} MHz",
|
||||
clocks.cpu_6x4x() / 1_000_000,
|
||||
clocks.cpu_3x2x() / 1_000_000,
|
||||
clocks.cpu_2x() / 1_000_000,
|
||||
clocks.cpu_1x() / 1_000_000);
|
||||
|
||||
let eth = eth::Eth::default(HWADDR.clone());
|
||||
println!("Eth on");
|
||||
|
||||
const RX_LEN: usize = 2;
|
||||
let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
|
||||
let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN];
|
||||
// Number of transmission buffers (minimum is two because with
|
||||
// one, duplicate packet transmission occurs)
|
||||
const TX_LEN: usize = 2;
|
||||
let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
|
||||
let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN];
|
||||
let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
|
||||
//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
|
||||
let mut eth = eth.start_tx(
|
||||
// HACK
|
||||
unsafe { transmute(tx_descs.as_mut()) },
|
||||
unsafe { transmute(tx_buffers.as_mut()) },
|
||||
);
|
||||
|
||||
let ethernet_addr = EthernetAddress(HWADDR);
|
||||
// IP stack
|
||||
let local_addr = IpAddress::v4(10, 0, 0, 1);
|
||||
let mut ip_addrs = [IpCidr::new(local_addr, 24)];
|
||||
let mut neighbor_storage = [None; 16];
|
||||
let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
|
||||
let mut iface = EthernetInterfaceBuilder::new(&mut eth)
|
||||
.ethernet_addr(ethernet_addr)
|
||||
.ip_addrs(&mut ip_addrs[..])
|
||||
.neighbor_cache(neighbor_cache)
|
||||
.finalize();
|
||||
let mut sockets_storage = [
|
||||
None, None, None, None,
|
||||
None, None, None, None
|
||||
];
|
||||
let mut sockets = SocketSet::new(&mut sockets_storage[..]);
|
||||
|
||||
let mut time = 0u32;
|
||||
loop {
|
||||
time += 1;
|
||||
let timestamp = Instant::from_millis(time.into());
|
||||
|
||||
match iface.poll(&mut sockets, timestamp) {
|
||||
Ok(_) => {},
|
||||
Err(e) => {
|
||||
println!("poll error: {}", e);
|
||||
}
|
||||
}
|
||||
|
||||
// match eth.recv_next() {
|
||||
// Ok(Some(pkt)) => {
|
||||
// print!("eth: rx {} bytes", pkt.len());
|
||||
// for b in pkt.iter() {
|
||||
// print!(" {:02X}", b);
|
||||
// }
|
||||
// println!("");
|
||||
// }
|
||||
// Ok(None) => {}
|
||||
// Err(e) => {
|
||||
// println!("eth rx error: {:?}", e);
|
||||
// }
|
||||
// }
|
||||
|
||||
// match eth.send(512) {
|
||||
// Some(mut pkt) => {
|
||||
// let mut x = 0;
|
||||
// for b in pkt.iter_mut() {
|
||||
// *b = x;
|
||||
// x += 1;
|
||||
// }
|
||||
// println!("eth tx {} bytes", pkt.len());
|
||||
// }
|
||||
// None => println!("eth tx shortage"),
|
||||
// }
|
||||
}
|
||||
}
|
||||
|
||||
#[panic_handler]
|
||||
fn panic(info: &core::panic::PanicInfo) -> ! {
|
||||
println!("\nPanic: {}", info);
|
||||
|
||||
slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
|
||||
loop {}
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
pub unsafe extern "C" fn PrefetchAbort() {
|
||||
println!("PrefetchAbort");
|
||||
loop {}
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
pub unsafe extern "C" fn DataAbort() {
|
||||
println!("DataAbort");
|
||||
loop {}
|
||||
}
|
|
@ -1,9 +0,0 @@
|
|||
use crate::{println, zynq};
|
||||
|
||||
#[panic_handler]
|
||||
fn panic(info: &core::panic::PanicInfo) -> ! {
|
||||
println!("\nPanic: {}", info);
|
||||
|
||||
zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
|
||||
loop {}
|
||||
}
|
42
src/ram.rs
42
src/ram.rs
|
@ -1,42 +0,0 @@
|
|||
use core::cell::RefCell;
|
||||
use core::alloc::GlobalAlloc;
|
||||
use core::ptr::NonNull;
|
||||
use alloc::alloc::Layout;
|
||||
use linked_list_allocator::Heap;
|
||||
use crate::zynq::ddr::DdrRam;
|
||||
|
||||
#[global_allocator]
|
||||
static ALLOCATOR: HeapAlloc = HeapAlloc(RefCell::new(Heap::empty()));
|
||||
|
||||
/// LockedHeap doesn't locking properly
|
||||
struct HeapAlloc(RefCell<Heap>);
|
||||
|
||||
/// FIXME: unsound; lock properly
|
||||
unsafe impl Sync for HeapAlloc {}
|
||||
|
||||
unsafe impl GlobalAlloc for HeapAlloc {
|
||||
unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
|
||||
self.0.borrow_mut()
|
||||
.allocate_first_fit(layout)
|
||||
.ok()
|
||||
.map_or(0 as *mut u8, |allocation| allocation.as_ptr())
|
||||
}
|
||||
|
||||
unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
|
||||
self.0.borrow_mut()
|
||||
.deallocate(NonNull::new_unchecked(ptr), layout)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn init_alloc(ddr: &mut DdrRam) {
|
||||
unsafe {
|
||||
ALLOCATOR.0.borrow_mut()
|
||||
.init(ddr.ptr::<u8>() as usize, ddr.size());
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#[alloc_error_handler]
|
||||
fn alloc_error(_: core::alloc::Layout) -> ! {
|
||||
panic!("alloc_error")
|
||||
}
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
use volatile_register::RW;
|
||||
|
||||
use crate::{register, register_bit, register_bits};
|
||||
use crate::{register, register_bit, register_bits, register_bits_typed};
|
||||
|
||||
pub unsafe fn axi_hp0() -> &'static RegisterBlock {
|
||||
&*(0xF8008000 as *const _)
|
||||
|
|
|
@ -186,6 +186,7 @@ impl DdrRam {
|
|||
self.regs.mode_sts_reg.read().operating_mode()
|
||||
}
|
||||
|
||||
// TODO: move into trait
|
||||
pub fn ptr<T>(&mut self) -> *mut T {
|
||||
0x0010_0000 as *mut _
|
||||
}
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
use volatile_register::{RO, RW};
|
||||
use volatile_register::{RO, WO, RW};
|
||||
|
||||
use crate::{register, register_bit, register_bits_typed};
|
||||
use crate::{register, register_bit, register_bits, register_bits_typed};
|
||||
|
||||
#[repr(u8)]
|
||||
pub enum DataBusWidth {
|
||||
|
@ -170,8 +170,7 @@ register_bit!(ddrc_ctrl, powerdown_en, 1);
|
|||
register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
|
||||
// (ddrc_ctrl) ...
|
||||
|
||||
// Controller operation mode status
|
||||
register!(mode_sts_reg,
|
||||
ModeStsReg, RO, u32);
|
||||
/// Controller operation mode status
|
||||
register!(mode_sts_reg, ModeStsReg, RO, u32);
|
||||
register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
|
||||
// (mode_sts_reg) ...
|
||||
|
|
|
@ -337,17 +337,8 @@ impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescLis
|
|||
type TxToken = tx::Token<'a, 'tx>;
|
||||
|
||||
fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
|
||||
use smoltcp::phy::{DeviceCapabilities, ChecksumCapabilities, Checksum};
|
||||
|
||||
let mut checksum_caps = ChecksumCapabilities::default();
|
||||
checksum_caps.ipv4 = Checksum::Both;
|
||||
checksum_caps.tcp = Checksum::Both;
|
||||
checksum_caps.udp = Checksum::Both;
|
||||
|
||||
let mut caps = DeviceCapabilities::default();
|
||||
let mut caps = smoltcp::phy::DeviceCapabilities::default();
|
||||
caps.max_transmission_unit = MTU;
|
||||
caps.checksum = checksum_caps;
|
||||
|
||||
caps
|
||||
}
|
||||
|
||||
|
@ -466,8 +457,6 @@ impl<'r> EthInner<'r> {
|
|||
.copy_all(true)
|
||||
// Remove 4-byte Frame CheckSum
|
||||
.fcs_remove(true)
|
||||
// RX checksum offload
|
||||
.rx_chksum_offld_en(true)
|
||||
// One of the slower speeds
|
||||
.mdc_clk_div((mdc_clk_div >> 4).min(0b111) as u8)
|
||||
);
|
||||
|
@ -498,7 +487,6 @@ impl<'r> EthInner<'r> {
|
|||
.rx_pktbuf_memsz_sel(0x3)
|
||||
// 4 KB
|
||||
.tx_pktbuf_memsz_sel(true)
|
||||
// TX checksum offload
|
||||
.csum_gen_offload_en(true)
|
||||
// Little-endian
|
||||
.ahb_endian_swp_mgmt_en(false)
|
||||
|
|
Loading…
Reference in New Issue