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No commits in common. "c3502888f205f9cea67e4010e4f2fccdfecfd629" and "8e09947c541d5671b7902408b03fd921e43889e6" have entirely different histories.

5 changed files with 8 additions and 8 deletions

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@ -14,6 +14,6 @@ lto = false
panic = "abort"
debug = true
# Link-Time Optimization:
# turn off if you get unusable debug symbols.
lto = true
# turned off for producing unusable debug symbols.
lto = false
opt-level = 'z' # Optimize for size.

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@ -1,5 +1,3 @@
#![cfg(feature = "target_zc706")]
use libboard_zynq::println;
mod zc706;
@ -7,8 +5,8 @@ mod zc706;
#[cfg(feature = "target_zc706")]
use zc706 as target;
// #[cfg(feature = "target_cora_z7_10")]
// use cora_z7_10 as target;
#[cfg(feature = "target_cora_z7_10")]
use cora_z7_10 as target;
pub fn report_differences() {
for (i, op) in target::INIT_DATA.iter().enumerate() {

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@ -1,3 +1,5 @@
use volatile_register::{RO, WO, RW};
use libregister::{
register, register_at,
register_bit, register_bits, register_bits_typed,

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@ -328,7 +328,7 @@ impl Flash<()> {
.mode_bits(0xFF)
// 2 devices
.two_mem(true)
.u_page(chip_index != 0)
.u_page(false)
// Quad SPI mode
.lq_mode(false)
);

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@ -142,7 +142,7 @@ impl<S: AsMut<[u32]>> Core1<S> {
// Ensure stack pointer has been written to cache
asm::dmb();
// Flush cache-line
cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as usize);
cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as u32);
// wake up core1
slcr::RegisterBlock::unlocked(|slcr| {