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No commits in common. "afd96bd887b5ca3972b9713f9d72a02ddd5a34dc" and "6e50b32e80749d5ce36003730dbf30bd36cf6eb2" have entirely different histories.
afd96bd887
...
6e50b32e80
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@ -90,30 +90,6 @@ impl CpuClocks {
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pll / u32::from(uart_clk_ctrl.divisor())
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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pub fn enable_io(target_clock: u32) {
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let fdiv = (target_clock / PS_CLK).min(66) as u16;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_bypass_force(true)
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.pll_fdiv(fdiv)
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);
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_reset(true)
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);
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_reset(false)
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);
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while ! slcr.pll_status.read().io_pll_lock() {}
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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);
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});
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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/// 25.10.4 PLLs
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pub fn enable_ddr(target_clock: u32) {
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pub fn enable_ddr(target_clock: u32) {
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@ -123,30 +99,29 @@ impl CpuClocks {
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.nth(0)
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.nth(0)
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.expect("PLL_FDIV_LOCK_PARAM")
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.expect("PLL_FDIV_LOCK_PARAM")
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.1.clone();
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.1.clone();
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slcr::RegisterBlock::unlocked(|regs| {
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let slcr = slcr::RegisterBlock::new();
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regs.ddr_pll_ctrl.modify(|_, w| w
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slcr.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_pwrdwn(false)
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.pll_bypass_force(true)
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.pll_bypass_force(true)
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.pll_fdiv(fdiv)
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.pll_fdiv(fdiv)
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);
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);
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regs.ddr_pll_cfg.write(
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slcr.ddr_pll_cfg.write(
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slcr::PllCfg::zeroed()
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slcr::PllCfg::zeroed()
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.pll_res(pll_res)
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.pll_res(pll_res)
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.pll_cp(pll_cp)
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.pll_cp(pll_cp)
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.lock_cnt(lock_cnt)
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.lock_cnt(lock_cnt)
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);
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);
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regs.ddr_pll_ctrl.modify(|_, w| w
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slcr.ddr_pll_ctrl.modify(|_, w| w
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.pll_reset(true)
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.pll_reset(true)
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);
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);
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regs.ddr_pll_ctrl.modify(|_, w| w
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slcr.ddr_pll_ctrl.modify(|_, w| w
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.pll_reset(false)
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.pll_reset(false)
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);
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);
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while ! regs.pll_status.read().ddr_pll_lock() {}
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while ! slcr.pll_status.read().ddr_pll_lock() {}
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regs.ddr_pll_ctrl.modify(|_, w| w
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slcr.ddr_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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.pll_bypass_qual(false)
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);
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);
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});
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}
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}
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}
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}
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@ -36,17 +36,13 @@ impl DdrRam {
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/// 10.6.1 DDR Clock Initialization
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup() -> CpuClocks {
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fn clock_setup() -> CpuClocks {
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let clocks = CpuClocks::get();
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let clocks = CpuClocks::get();
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if clocks.ddr == 0 {
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CpuClocks::enable_ddr(clocks.arm);
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CpuClocks::enable_ddr(clocks.arm);
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}
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let clocks = CpuClocks::get();
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let clocks = CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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let ddr3x_clk_divisor = ((DDR_FREQ - 1 + clocks.ddr) / DDR_FREQ).min(255) as u8;
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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slcr.ddr_clk_ctrl.write(
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slcr.ddr_clk_ctrl.write(
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slcr::DdrClkCtrl::zeroed()
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slcr::DdrClkCtrl::zeroed()
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.ddr_2xclkact(true)
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.ddr_2xclkact(true)
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@ -54,7 +50,6 @@ impl DdrRam {
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.ddr_2xclk_divisor(ddr2x_clk_divisor)
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.ddr_2xclk_divisor(ddr2x_clk_divisor)
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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);
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);
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});
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clocks
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clocks
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}
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}
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@ -65,9 +60,8 @@ impl DdrRam {
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.max(1).min(63) as u8;
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.max(1).min(63) as u8;
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let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
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let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
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.max(1).min(63) as u8;
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.max(1).min(63) as u8;
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println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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// Step 1.
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// Step 1.
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slcr.dci_clk_ctrl.write(
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slcr.dci_clk_ctrl.write(
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slcr::DciClkCtrl::zeroed()
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slcr::DciClkCtrl::zeroed()
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@ -101,13 +95,12 @@ impl DdrRam {
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);
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);
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// Step 2.e.
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// Step 2.e.
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while ! slcr.ddriob_dci_status.read().done() {}
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while ! slcr.ddriob_dci_status.read().done() {}
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});
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}
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.3 DDR IOB Configuration
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/// 10.6.3 DDR IOB Configuration
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fn configure_iob() {
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fn configure_iob() {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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let addr_config = slcr::DdriobConfig::zeroed()
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let addr_config = slcr::DdriobConfig::zeroed()
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.output_en(slcr::DdriobOutputEn::Obuf);
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.output_en(slcr::DdriobOutputEn::Obuf);
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slcr.ddriob_addr0.write(addr_config.clone());
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slcr.ddriob_addr0.write(addr_config.clone());
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@ -161,7 +154,6 @@ impl DdrRam {
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.vref_sel(vref_sel)
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.vref_sel(vref_sel)
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.vref_int_en(false)
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.vref_int_en(false)
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);
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);
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});
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}
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}
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/// Reset DDR controller
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/// Reset DDR controller
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@ -27,7 +27,7 @@ pub struct Eth<'r, RX, TX> {
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impl<'r> Eth<'r, (), ()> {
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impl<'r> Eth<'r, (), ()> {
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pub fn default(macaddr: [u8; 6]) -> Self {
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pub fn default(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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// Manual example: 0x0000_1280
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// Manual example: 0x0000_1280
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// MDIO
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// MDIO
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slcr.mio_pin_53.write(
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slcr.mio_pin_53.write(
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@ -152,7 +152,6 @@ impl<'r> Eth<'r, (), ()> {
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slcr::GpiobCtrl::zeroed()
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slcr::GpiobCtrl::zeroed()
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.vref_en(true)
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.vref_en(true)
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);
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);
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});
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Self::gem0(macaddr)
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Self::gem0(macaddr)
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}
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}
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@ -198,7 +197,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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slcr.gem0_clk_ctrl.write(
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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// 0x0050_0801: 8, 5: 100 Mb/s
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// ...: 8, 1: 1000 Mb/s
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// ...: 8, 1: 1000 Mb/s
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@ -214,7 +213,6 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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slcr::RclkCtrl::zeroed()
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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.clkact(true)
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);
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);
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});
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}
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}
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pub fn setup_gem1_clock(tx_clock: u32) {
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pub fn setup_gem1_clock(tx_clock: u32) {
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@ -222,7 +220,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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let d1 = (io_pll / tx_clock / d0).max(1).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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slcr.gem1_clk_ctrl.write(
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slcr.gem1_clk_ctrl.write(
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slcr::GemClkCtrl::zeroed()
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.clkact(true)
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@ -236,7 +234,6 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
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slcr::RclkCtrl::zeroed()
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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.clkact(true)
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);
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);
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});
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}
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}
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pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {
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pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {
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@ -247,7 +247,8 @@ pub struct RegisterBlock {
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register_at!(RegisterBlock, 0xF8000000, new);
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register_at!(RegisterBlock, 0xF8000000, new);
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impl RegisterBlock {
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impl RegisterBlock {
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/// Required to modify any sclr register
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/// Required to modify these sclr registers: scl, pss_rst_ctrl,
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/// apu_ctrl, and wdt_clk_sel
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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let mut self_ = Self::new();
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let mut self_ = Self::new();
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self_.slcr_unlock.unlock();
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self_.slcr_unlock.unlock();
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@ -14,7 +14,7 @@ pub struct Uart {
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impl Uart {
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impl Uart {
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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pub fn serial(baudrate: u32) -> Self {
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pub fn serial(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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// Route UART 1 RxD/TxD Signals to MIO Pins
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// Route UART 1 RxD/TxD Signals to MIO Pins
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// TX pin
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// TX pin
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slcr.mio_pin_48.write(
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slcr.mio_pin_48.write(
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@ -31,13 +31,12 @@ impl Uart {
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.io_type(slcr::IoBufferType::Lvcmos18)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.pullup(true)
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);
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);
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});
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Self::uart1(baudrate)
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Self::uart1(baudrate)
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}
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}
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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pub fn serial(baudrate: u32) -> Self {
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pub fn serial(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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// Route UART 0 RxD/TxD Signals to MIO Pins
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// Route UART 0 RxD/TxD Signals to MIO Pins
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// TX pin
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// TX pin
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slcr.mio_pin_15.write(
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slcr.mio_pin_15.write(
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@ -54,16 +53,14 @@ impl Uart {
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.io_type(slcr::IoBufferType::Lvcmos33)
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.io_type(slcr::IoBufferType::Lvcmos33)
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.pullup(true)
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.pullup(true)
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);
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);
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});
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Self::uart0(baudrate)
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Self::uart0(baudrate)
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}
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}
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pub fn uart0(baudrate: u32) -> Self {
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pub fn uart0(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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slcr.uart_rst_ctrl.reset_uart0();
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slcr.uart_rst_ctrl.reset_uart0();
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slcr.aper_clk_ctrl.enable_uart0();
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slcr.aper_clk_ctrl.enable_uart0();
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slcr.uart_clk_ctrl.enable_uart0();
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slcr.uart_clk_ctrl.enable_uart0();
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});
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let mut self_ = Uart {
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let mut self_ = Uart {
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regs: regs::RegisterBlock::uart0(),
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regs: regs::RegisterBlock::uart0(),
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};
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};
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@ -72,11 +69,10 @@ impl Uart {
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}
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}
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pub fn uart1(baudrate: u32) -> Self {
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pub fn uart1(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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let slcr = slcr::RegisterBlock::new();
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slcr.uart_rst_ctrl.reset_uart1();
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slcr.uart_rst_ctrl.reset_uart1();
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slcr.aper_clk_ctrl.enable_uart1();
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slcr.aper_clk_ctrl.enable_uart1();
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slcr.uart_clk_ctrl.enable_uart1();
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slcr.uart_clk_ctrl.enable_uart1();
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});
|
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let mut self_ = Uart {
|
let mut self_ = Uart {
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regs: regs::RegisterBlock::uart1(),
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regs: regs::RegisterBlock::uart1(),
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};
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};
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|
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Reference in New Issue