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2 changed files with 78 additions and 11 deletions

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@ -1,5 +1,6 @@
//! Quad-SPI Flash Controller
use core::marker::PhantomData;
use crate::regs::{RegisterW, RegisterRW};
use super::slcr;
use super::clocks::CpuClocks;
@ -8,23 +9,25 @@ pub mod regs;
const FLASH_BAUD_RATE: u32 = 50_000_000;
pub struct LinearAddressing;
/// Flash Interface Driver
///
/// For 2x Spansion S25FL128SAGMFIR01
pub struct Flash {
pub struct Flash<MODE> {
regs: &'static mut regs::RegisterBlock,
_mode: PhantomData<MODE>,
}
impl Flash {
impl Flash<()> {
pub fn new(clock: u32) -> Self {
Self::enable_clocks(clock);
Self::setup_signals();
Self::reset();
let regs = regs::RegisterBlock::qspi();
let mut flash = Flash { regs };
let mut flash = Flash { regs, _mode: PhantomData };
flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
flash.setup_linear_addressing_mode();
flash
}
@ -82,7 +85,53 @@ impl Flash {
.io_type(slcr::IoBufferType::Lvcmos18)
);
// TODO: optional 2nd chip setup
// Option: Add Second Device Chip Select
// 4. Configure MIO pin 0 for chip select 1 output.
slcr.mio_pin_00.write(
slcr::MioPin00::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true)
);
// Option: Add Second Serial Clock
// 5. Configure MIO pin 9 for serial clock 1 output.
slcr.mio_pin_09.write(
slcr::MioPin09::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
// Option: Add 4-bit Data
// 6. Configure MIO pins 10 through 13 for I/O.
slcr.mio_pin_10.write(
slcr::MioPin10::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
slcr.mio_pin_11.write(
slcr::MioPin11::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
slcr.mio_pin_12.write(
slcr::MioPin12::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
slcr.mio_pin_13.write(
slcr::MioPin13::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
// Option: Add Feedback Output Clock
// 7. Configure MIO pin 8 for feedback clock.
slcr.mio_pin_08.write(
slcr::MioPin08::zeroed()
.l0_sel(true)
.io_type(slcr::IoBufferType::Lvcmos18)
);
});
}
@ -106,25 +155,40 @@ impl Flash {
baud_rate_div += 1;
}
self.regs.config.modify(|_, w| w
self.regs.config.write(regs::Config::zeroed()
.baud_rate_div(baud_rate_div as u8)
.mode_sel(true)
.leg_flsh(true)
.endian(false)
.fifo_width(0b11)
);
}
fn setup_linear_addressing_mode(&mut self) {
self.regs.lqspi_cfg.modify(|_, w| w
pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
// Set manual start enable to auto mode.
// Assert the chip select.
self.regs.config.modify(|_, w| w
.man_start_en(false)
.pcs(false)
);
self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
.inst_code(0x3)
.u_page(false)
.sep_bus(false)
.two_mem(false)
.lq_mode(true)
);
}
self.regs.enable.modify(|_, w| w.spi_en(true));
Flash {
regs: self.regs,
_mode: PhantomData,
}
}
}
impl Flash<LinearAddressing> {
pub fn ptr<T>(&mut self) -> *mut T {
0xFC00_0000 as *mut _
}

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@ -9,7 +9,7 @@ pub struct RegisterBlock {
pub intr_en: RW<u32>,
pub intr_dis: RW<u32>,
pub intr_mask: RO<u32>,
pub enable: RW<u32>,
pub enable: Enable,
pub delay: RW<u32>,
pub txd0: WO<u32>,
pub rx_data: RO<u32>,
@ -77,6 +77,9 @@ register_bit!(config,
/// false: legacy SPI mode, true: Flash memory interface mode
leg_flsh, 31);
register!(enable, Enable, RW, u32);
register_bit!(enable, spi_en, 0);
register!(lqspi_cfg, LqspiCfg, RW, u32);
register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10);