src/zynq/ddr/mod.rs

@@ -169,14 +169,10 @@ impl DdrRam {
         self.regs.ddrc_ctrl.modify(|_, w| w
             .soft_rstb(false)
         );
-        #[cfg(feature = "target_zc706")]
-        let width = regs::DataBusWidth::Width32bit;
-        #[cfg(feature = "target_cora_z7_10")]
-        let width = regs::DataBusWidth::Width16bit;
         self.regs.ddrc_ctrl.modify(|_, w| w
             .soft_rstb(true)
             .powerdown_en(false)
-            .data_bus_width(width)
+            .data_bus_width(regs::DataBusWidth::Width32bit)
         );
 
         while self.status() == regs::ControllerStatus::Init {}

src/zynq/eth/mod.rs

@@ -507,12 +507,6 @@ impl<'r> EthInner<'r> {
 
 
     fn check_link_change(&mut self, phy: &Phy) {
-        // As the PHY access takes some time, exit early if there was
-        // already a link. TODO: check once per second.
-        if self.link.is_some() {
-            return
-        }
-
         let link = phy.get_link(self);
 
         // Check link state transition

src/zynq/eth/rx.rs

@@ -3,6 +3,8 @@ use vcell::VolatileCell;
 use crate::{register, register_bit, register_bits, regs::*};
 use super::MTU;
 
+use crate::cortex_a9::asm;
+
 #[derive(Debug)]
 pub enum Error {
     HrespNotOk,
@@ -77,6 +79,8 @@ impl<'a> DescList<'a> {
                 DescWord1::zeroed()
             );
         }
+        // Ensure descriptors get written before they are read.
+        asm::dmb();
 
         DescList {
             // Shorten the list of descriptors to the required number.
@@ -96,6 +100,7 @@ impl<'a> DescList<'a> {
         if entry.word0.read().used() {
             let word1 = entry.word1.read();
             let len = word1.frame_length_lsbs().into();
+            asm::dmb();
             let buffer = &mut self.buffers[self.next][0..len];
 
             self.next += 1;
@@ -123,6 +128,9 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
+        // Ensure that any buffer reads have finished before we
+        // release the buffer to the hardware.
+        asm::dmb();
         self.entry.word0.modify(|_, w| w.used(false));
     }
 }

src/zynq/eth/tx.rs

@@ -1,6 +1,7 @@
 use core::ops::{Deref, DerefMut};
 use vcell::VolatileCell;
 use crate::{register, register_bit, register_bits, regs::*};
+use crate::cortex_a9::asm;
 use super::{MTU, regs};
 
 /// Descriptor entry
@@ -72,6 +73,8 @@ impl<'a> DescList<'a> {
                     .last_buffer(true)
             );
         }
+        // Ensure the descriptor words get written before they are read.
+        asm::dsb();
 
         DescList {
             // Shorten the list of descriptors to the required number.
@@ -120,7 +123,14 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
+        // Ensure that all writes to the buffer have finished before
+        // they are read again.
+        asm::dmb();
         self.entry.word1.modify(|_, w| w.used(false));
+        // Ensure that the descriptor write has finished before it is
+        // read again, and (by DSB, not just DMB) that it has been
+        // written before the register access.
+        asm::dsb();
         if ! self.regs.tx_status.read().tx_go() {
             self.regs.net_ctrl.modify(|_, w|
                                       w.start_tx(true)