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55f8d02da8
Author | SHA1 | Date |
---|---|---|
Astro | 55f8d02da8 | |
Astro | 990fa56d6a |
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@ -143,8 +143,6 @@ pub fn main_core0() {
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let timer = libboard_zynq::timer::GlobalTimer::start();
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let timer = libboard_zynq::timer::GlobalTimer::start();
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let mut ddr = zynq::ddr::DdrRam::ddrram();
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let mut ddr = zynq::ddr::DdrRam::ddrram();
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// ddr init may call ps7_init, reconfiguring the uart
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libboard_zynq::stdio::drop_uart();
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#[cfg(not(feature = "target_zc706"))]
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#[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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ram::init_alloc_ddr(&mut ddr);
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@ -1,12 +1,9 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{debug, info, error};
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use log::{debug, info, error};
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use crate::{print, println};
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use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::slcr;
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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#[cfg(feature = "target_redpitaya")]
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use super::ps7_init;
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mod regs;
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mod regs;
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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@ -18,8 +15,8 @@ const DDR_FREQ: u32 = 666_666_666;
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const DDR_FREQ: u32 = 525_000_000;
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const DDR_FREQ: u32 = 525_000_000;
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 800_000_000;
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const DDR_FREQ: u32 = 533_333_333;
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/// MT41K256M16HA-125
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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const DCI_FREQ: u32 = 10_000_000;
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@ -30,15 +27,6 @@ pub struct DdrRam {
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impl DdrRam {
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impl DdrRam {
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pub fn ddrram() -> Self {
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pub fn ddrram() -> Self {
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if cfg!(feature = "target_redpitaya") {
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// We have not yet fixed red pitaya initialization yet. It seems
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// that the clock configuration, iob settings and ddr settings are
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// all problematic
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#[cfg(feature = "target_redpitaya")]
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ps7_init::apply();
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let regs = regs::RegisterBlock::ddrc();
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DdrRam { regs }
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} else {
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let clocks = Self::clock_setup();
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let clocks = Self::clock_setup();
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Self::configure_iob();
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Self::configure_iob();
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Self::calibrate_iob_impedance(&clocks);
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Self::calibrate_iob_impedance(&clocks);
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@ -47,7 +35,6 @@ impl DdrRam {
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ddr.reset_ddrc(|ddr| ddr.configure());
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ddr.reset_ddrc(|ddr| ddr.configure());
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ddr
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ddr
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}
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}
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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/// 10.6.1 DDR Clock Initialization
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@ -237,6 +224,7 @@ impl DdrRam {
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.vref_int_en(false)
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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.vref_ext_en_upper(false)
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.refio_en(true)
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);
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);
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});
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});
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}
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}
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@ -249,6 +237,13 @@ impl DdrRam {
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.t_rfc_min(0x9e)
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.t_rfc_min(0x9e)
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.post_selfref_gap_x32(0x10)
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.post_selfref_gap_x32(0x10)
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);
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1b)
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.t_rfc_min(0xa0)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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self.regs.dram_param0.write(
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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regs::DramParam0::zeroed()
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@ -256,6 +251,16 @@ impl DdrRam {
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.t_rfc_min(0x56)
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.t_rfc_min(0x56)
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.post_selfref_gap_x32(0x10)
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.post_selfref_gap_x32(0x10)
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);
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param1.modify(
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|_, w| w
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.wr2pre(0x12)
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.powerdown_to_x32(6)
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.t_faw(0x16)
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.t_ras_max(0x24)
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.t_ras_min(0x13)
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.t_cke(4)
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);
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self.regs.dram_param2.write(
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self.regs.dram_param2.write(
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regs::DramParam2::zeroed()
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regs::DramParam2::zeroed()
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@ -267,6 +272,20 @@ impl DdrRam {
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.rd2pre(0x4)
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.rd2pre(0x4)
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.t_rcd(0x7)
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.t_rcd(0x7)
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);
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param3.modify(
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|_, w| w
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.t_ccd(4)
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.t_rrd(6)
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.refresh_margin(2)
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.t_rp(7)
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.refresh_to_x32(8)
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.mobile(false)
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.dfi_dram_clk_disable(false)
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.read_latency(7)
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.mode_ddr1_ddr2(true)
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.dis_pad_pd(false)
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);
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self.regs.dram_emr_mr.write(
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self.regs.dram_emr_mr.write(
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regs::DramEmrMr::zeroed()
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regs::DramEmrMr::zeroed()
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@ -275,11 +294,19 @@ impl DdrRam {
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);
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);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config2.modify(
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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|_, w| w.data_slice_in_use(false)
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);
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);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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self.regs.phy_config3.modify(
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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|_, w| w.data_slice_in_use(false)
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);
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);
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@ -316,7 +343,7 @@ impl DdrRam {
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);
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);
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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self.regs.phy_init_ratio3.write(
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self.regs.phy_init_ratios[3].write(
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regs::PhyInitRatio::zeroed()
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regs::PhyInitRatio::zeroed()
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.wrlvl_init_ratio(0x21)
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.wrlvl_init_ratio(0x21)
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.gatelvl_init_ratio(0xee)
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.gatelvl_init_ratio(0xee)
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@ -328,6 +355,18 @@ impl DdrRam {
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.phy_ctrl_slave_ratio(0x100)
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.phy_ctrl_slave_ratio(0x100)
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.phy_invert_clkout(true)
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.phy_invert_clkout(true)
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);
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.reg_64.modify(
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|_, w| w
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.phy_bl2(false)
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.phy_invert_clkout(true)
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.phy_sel_logic(false)
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.phy_ctrl_slave_ratio(0x100)
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.phy_ctrl_slave_force(false)
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.phy_ctrl_slave_delay(0)
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.phy_lpddr(false)
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.phy_cmd_latency(false)
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);
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self.regs.reg_65.write(
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self.regs.reg_65.write(
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regs::Reg65::zeroed()
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regs::Reg65::zeroed()
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@ -364,7 +403,7 @@ impl DdrRam {
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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}
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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unsafe {
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unsafe {
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// row/column address bits
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000666);
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self.regs.dram_addr_map_bank.write(0x00000666);
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@ -60,7 +60,7 @@ pub struct RegisterBlock {
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pub ctrl6: RW<u32>,
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pub ctrl6: RW<u32>,
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_unused1: [RO<u32>; 8],
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_unused1: [RO<u32>; 8],
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pub che_refresh_timer01: RW<u32>,
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pub che_refresh_timer01: RW<u32>,
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pub che_t_zq: RW<u32>,
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pub che_t_zq: CheTZq,
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pub che_t_zq_short_interval: RW<u32>,
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pub che_t_zq_short_interval: RW<u32>,
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pub deep_pwrdwn: RW<u32>,
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pub deep_pwrdwn: RW<u32>,
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pub reg_2c: Reg2C,
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pub reg_2c: Reg2C,
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@ -84,15 +84,9 @@ pub struct RegisterBlock {
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pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
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pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
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_unused3: [RO<u32>; 5],
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_unused3: [RO<u32>; 5],
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pub phy_rcvr_enable: RW<u32>,
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pub phy_rcvr_enable: RW<u32>,
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pub phy_config0: PhyConfig,
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pub phy_configs: [PhyConfig; 4],
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pub phy_config1: PhyConfig,
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pub phy_config2: PhyConfig,
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pub phy_config3: PhyConfig,
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_unused4: RO<u32>,
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_unused4: RO<u32>,
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pub phy_init_ratio0: PhyInitRatio,
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pub phy_init_ratios: [PhyInitRatio; 4],
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pub phy_init_ratio1: PhyInitRatio,
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pub phy_init_ratio2: PhyInitRatio,
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pub phy_init_ratio3: PhyInitRatio,
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_unused5: RO<u32>,
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_unused5: RO<u32>,
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pub phy_rd_dqs_cfg0: RW<u32>,
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pub phy_rd_dqs_cfg0: RW<u32>,
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pub phy_rd_dqs_cfg1: RW<u32>,
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pub phy_rd_dqs_cfg1: RW<u32>,
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@ -138,10 +132,7 @@ pub struct RegisterBlock {
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_unused14: [RO<u32>; 5],
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_unused14: [RO<u32>; 5],
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pub axi_id: RW<u32>,
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pub axi_id: RW<u32>,
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pub page_mask: RW<u32>,
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pub page_mask: RW<u32>,
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pub axi_priority_wr_port0: RW<u32>,
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pub axi_priority_wr_ports: [RW<u32>; 4],
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pub axi_priority_wr_port1: RW<u32>,
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pub axi_priority_wr_port2: RW<u32>,
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pub axi_priority_wr_port3: RW<u32>,
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pub axi_priority_rd_ports: [AxiPriorityRd; 4],
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pub axi_priority_rd_ports: [AxiPriorityRd; 4],
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_unused15: [RO<u32>; 27],
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_unused15: [RO<u32>; 27],
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pub excl_access_cfg0: RW<u32>,
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pub excl_access_cfg0: RW<u32>,
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@ -222,6 +213,13 @@ register_bit!(phy_cmd_timeout_rddata_cpt, clk_stall_level, 19);
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register_bits!(phy_cmd_timeout_rddata_cpt, gatelvl_num_of_dq0, u8, 24, 27);
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register_bits!(phy_cmd_timeout_rddata_cpt, gatelvl_num_of_dq0, u8, 24, 27);
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register_bits!(phy_cmd_timeout_rddata_cpt, wrlvl_num_of_dq0, u8, 28, 31);
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register_bits!(phy_cmd_timeout_rddata_cpt, wrlvl_num_of_dq0, u8, 28, 31);
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register!(che_t_zq, CheTZq, RW, u32);
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register_bit!(che_t_zq, dis_auto_zq, 0);
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register_bit!(che_t_zq, ddr3, 1);
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register_bits!(che_t_zq, t_mod, u8, 2, 11);
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register_bits!(che_t_zq, t_zq_long_nop, u16, 12, 21);
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register_bits!(che_t_zq, t_zq_short_nop, u16, 22, 31);
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register!(reg_2c, Reg2C, RW, u32);
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register!(reg_2c, Reg2C, RW, u32);
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register_bits!(reg_2c, wrlvl_max_x1024, u16, 0, 11);
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register_bits!(reg_2c, wrlvl_max_x1024, u16, 0, 11);
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register_bits!(reg_2c, rdlvl_max_x1024, u16, 12, 23);
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register_bits!(reg_2c, rdlvl_max_x1024, u16, 12, 23);
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@ -3,16 +3,12 @@ use crate::println;
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#[cfg(feature = "target_zc706")]
|
#[cfg(feature = "target_zc706")]
|
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mod zc706;
|
mod zc706;
|
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#[cfg(feature = "target_redpitaya")]
|
#[cfg(not(feature = "target_zc706"))]
|
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mod redpitaya;
|
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))]
|
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mod none;
|
mod none;
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|
|
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#[cfg(feature = "target_zc706")]
|
#[cfg(feature = "target_zc706")]
|
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use zc706 as target;
|
use zc706 as target;
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#[cfg(feature = "target_redpitaya")]
|
#[cfg(not(feature = "target_zc706"))]
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use redpitaya as target;
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|
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#[cfg(not(any(feature = "target_zc706", feature = "target_redpitaya")))]
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use none as target;
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use none as target;
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|
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pub fn report_differences() {
|
pub fn report_differences() {
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|
|
|
@ -1,106 +0,0 @@
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use super::InitOp::{self, *};
|
|
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|
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pub const INIT_DATA: &'static [InitOp] = &[
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MaskWrite(0xF8000008, 0xFFFFFFFF, 0x0000DF0D),
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MaskWrite(0xF8000124, 0xFFF00003 ,0x0C200003),
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MaskWrite(0xF8000B40, 0x00000FFF, 0x00000600),
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MaskWrite(0xF8000B44, 0x00000FFF, 0x00000600),
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MaskWrite(0xF8000B48, 0x00000FFF, 0x00000672),
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MaskWrite(0xF8000B4C, 0x00000FFF, 0x00000800),
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|
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MaskWrite(0xF8000B50, 0x00000FFF, 0x00000674),
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|
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MaskWrite(0xF8000B54, 0x00000FFF, 0x00000800),
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|
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MaskWrite(0xF8000B58, 0x00000FFF, 0x00000600),
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|
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MaskWrite(0xF8000B5C, 0xFFFFFFFF, 0x0018C61C),
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|
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MaskWrite(0xF8000B60, 0xFFFFFFFF, 0x00F9861C),
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|
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MaskWrite(0xF8000B64, 0xFFFFFFFF, 0x00F9861C),
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|
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MaskWrite(0xF8000B68, 0xFFFFFFFF, 0x00F9861C),
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|
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MaskWrite(0xF8000B6C, 0x00007FFF, 0x00000220),
|
|
||||||
MaskWrite(0xF8000B70, 0x00000001, 0x00000001),
|
|
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MaskWrite(0xF8000B70, 0x00000021, 0x00000020),
|
|
||||||
MaskWrite(0xF8000B70, 0x07FEFFFF, 0x00000823),
|
|
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MaskWrite(0xF8000700, 0x00003FFF, 0x00001600),
|
|
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MaskWrite(0xF8000704, 0x00003FFF, 0x00001602),
|
|
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MaskWrite(0xF8000004, 0xFFFFFFFF, 0x0000767B),
|
|
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MaskWrite(0xF8006000, 0x0001FFFF, 0x00000084),
|
|
||||||
MaskWrite(0xF8006004, 0x0007FFFF, 0x00001081),
|
|
||||||
MaskWrite(0xF8006008, 0x03FFFFFF, 0x03C0780F),
|
|
||||||
MaskWrite(0xF800600C, 0x03FFFFFF, 0x02001001),
|
|
||||||
MaskWrite(0xF8006010, 0x03FFFFFF, 0x00014001),
|
|
||||||
MaskWrite(0xF8006014, 0x001FFFFF, 0x0004281B),
|
|
||||||
MaskWrite(0xF8006018, 0xF7FFFFFF, 0x44E458D2),
|
|
||||||
MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5),
|
|
||||||
MaskWrite(0xF8006020, 0x7FDFFFFC, 0x270872D0),
|
|
||||||
MaskWrite(0xF8006024, 0x0FFFFFC3, 0x00000000),
|
|
||||||
MaskWrite(0xF8006028, 0x00003FFF, 0x00002007),
|
|
||||||
MaskWrite(0xF800602C, 0xFFFFFFFF, 0x00000008),
|
|
||||||
MaskWrite(0xF8006030, 0xFFFFFFFF, 0x00040930),
|
|
||||||
MaskWrite(0xF8006034, 0x13FF3FFF, 0x000116D4),
|
|
||||||
MaskWrite(0xF8006038, 0x00000003, 0x00000000),
|
|
||||||
MaskWrite(0xF800603C, 0x000FFFFF, 0x00000666),
|
|
||||||
MaskWrite(0xF8006040, 0xFFFFFFFF, 0xFFFF0000),
|
|
||||||
MaskWrite(0xF8006044, 0x0FFFFFFF, 0x0F555555),
|
|
||||||
MaskWrite(0xF8006048, 0x0003F03F, 0x0003C008),
|
|
||||||
MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800),
|
|
||||||
MaskWrite(0xF8006058, 0x00010000, 0x00000000),
|
|
||||||
MaskWrite(0xF800605C, 0x0000FFFF, 0x00005003),
|
|
||||||
MaskWrite(0xF8006060, 0x000017FF, 0x0000003E),
|
|
||||||
MaskWrite(0xF8006064, 0x00021FE0, 0x00020000),
|
|
||||||
MaskWrite(0xF8006068, 0x03FFFFFF, 0x00284141),
|
|
||||||
MaskWrite(0xF800606C, 0x0000FFFF, 0x00001610),
|
|
||||||
MaskWrite(0xF8006078, 0x03FFFFFF, 0x00466111),
|
|
||||||
MaskWrite(0xF800607C, 0x000FFFFF, 0x00032222),
|
|
||||||
MaskWrite(0xF80060A4, 0xFFFFFFFF, 0x10200802),
|
|
||||||
MaskWrite(0xF80060A8, 0x0FFFFFFF, 0x0690CB73),
|
|
||||||
MaskWrite(0xF80060AC, 0x000001FF, 0x000001FE),
|
|
||||||
MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF),
|
|
||||||
MaskWrite(0xF80060B4, 0x00000200, 0x00000200),
|
|
||||||
MaskWrite(0xF80060B8, 0x01FFFFFF, 0x00200066),
|
|
||||||
MaskWrite(0xF80060C4, 0x00000003, 0x00000000),
|
|
||||||
MaskWrite(0xF80060C8, 0x000000FF, 0x00000000),
|
|
||||||
MaskWrite(0xF80060DC, 0x00000001, 0x00000000),
|
|
||||||
MaskWrite(0xF80060F0, 0x0000FFFF, 0x00000000),
|
|
||||||
MaskWrite(0xF80060F4, 0x0000000F, 0x00000008),
|
|
||||||
MaskWrite(0xF8006114, 0x000000FF, 0x00000000),
|
|
||||||
MaskWrite(0xF8006118, 0x7FFFFFCF, 0x40000001),
|
|
||||||
MaskWrite(0xF800611C, 0x7FFFFFCF, 0x40000001),
|
|
||||||
MaskWrite(0xF8006120, 0x7FFFFFCF, 0x40000000),
|
|
||||||
MaskWrite(0xF8006124, 0x7FFFFFCF, 0x40000000),
|
|
||||||
MaskWrite(0xF800612C, 0x000FFFFF, 0x00029000),
|
|
||||||
MaskWrite(0xF8006130, 0x000FFFFF, 0x00029000),
|
|
||||||
MaskWrite(0xF8006134, 0x000FFFFF, 0x00029000),
|
|
||||||
MaskWrite(0xF8006138, 0x000FFFFF, 0x00029000),
|
|
||||||
MaskWrite(0xF8006140, 0x000FFFFF, 0x00000035),
|
|
||||||
MaskWrite(0xF8006144, 0x000FFFFF, 0x00000035),
|
|
||||||
MaskWrite(0xF8006148, 0x000FFFFF, 0x00000035),
|
|
||||||
MaskWrite(0xF800614C, 0x000FFFFF, 0x00000035),
|
|
||||||
MaskWrite(0xF8006154, 0x000FFFFF, 0x00000080),
|
|
||||||
MaskWrite(0xF8006158, 0x000FFFFF, 0x00000080),
|
|
||||||
MaskWrite(0xF800615C, 0x000FFFFF, 0x00000080),
|
|
||||||
MaskWrite(0xF8006160, 0x000FFFFF, 0x00000080),
|
|
||||||
MaskWrite(0xF8006168, 0x001FFFFF, 0x000000F9),
|
|
||||||
MaskWrite(0xF800616C, 0x001FFFFF, 0x000000F9),
|
|
||||||
MaskWrite(0xF8006170, 0x001FFFFF, 0x000000F9),
|
|
||||||
MaskWrite(0xF8006174, 0x001FFFFF, 0x000000F9),
|
|
||||||
MaskWrite(0xF800617C, 0x000FFFFF, 0x000000C0),
|
|
||||||
MaskWrite(0xF8006180, 0x000FFFFF, 0x000000C0),
|
|
||||||
MaskWrite(0xF8006184, 0x000FFFFF, 0x000000C0),
|
|
||||||
MaskWrite(0xF8006188, 0x000FFFFF, 0x000000C0),
|
|
||||||
MaskWrite(0xF8006190, 0x6FFFFEFE, 0x00040080),
|
|
||||||
MaskWrite(0xF8006194, 0x000FFFFF, 0x0001FC82),
|
|
||||||
MaskWrite(0xF8006204, 0xFFFFFFFF, 0x00000000),
|
|
||||||
MaskWrite(0xF8006208, 0x000703FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF800620C, 0x000703FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF8006210, 0x000703FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF8006214, 0x000703FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF8006218, 0x000F03FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF800621C, 0x000F03FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF8006220, 0x000F03FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF8006224, 0x000F03FF, 0x000003FF),
|
|
||||||
MaskWrite(0xF80062A8, 0x00000FF5, 0x00000000),
|
|
||||||
MaskWrite(0xF80062AC, 0xFFFFFFFF, 0x00000000),
|
|
||||||
MaskWrite(0xF80062B0, 0x003FFFFF, 0x00005125),
|
|
||||||
MaskWrite(0xF80062B4, 0x0003FFFF, 0x000012A8),
|
|
||||||
MaskPoll(0xF8000B74, 0x00002000),
|
|
||||||
MaskWrite(0xF8006000, 0x0001FFFF, 0x00000085),
|
|
||||||
MaskPoll(0xF8006054, 0x00000007),
|
|
||||||
];
|
|
Loading…
Reference in New Issue