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2 Commits
6bee1f44f4 ... 961e2e1dd0

Author SHA1 Message Date
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation 
off-by-one, didn't change behavior.
 2019-11-03 02:23:16 +01:00
Astro 04e816d99e zynq::slcr: fix a bitfield index 
that didn't solve our problems.
 2019-11-03 02:01:42 +01:00
3 changed files with 7 additions and 7 deletions
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4
src/zynq/ddr/mod.rs
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@ -56,9 +56,9 @@ impl DdrRam {
/// Zynq-7000 AP SoC Technical Reference Manual: /// Zynq-7000 AP SoC Technical Reference Manual:
/// 10.6.2 DDR IOB Impedance Calibration /// 10.6.2 DDR IOB Impedance Calibration
fn calibrate_iob_impedance(clocks: &CpuClocks) { fn calibrate_iob_impedance(clocks: &CpuClocks) {
let divisor0 = (clocks.ddr / DCI_FREQ) let divisor0 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ)
.max(1).min(63) as u8; .max(1).min(63) as u8;
let divisor1 = 1 + (clocks.ddr / DCI_FREQ / u32::from(divisor0)) let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
.max(1).min(63) as u8; .max(1).min(63) as u8;
let slcr = slcr::RegisterBlock::new(); let slcr = slcr::RegisterBlock::new();

8
src/zynq/eth/mod.rs
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@ -192,8 +192,8 @@ impl<'r> Eth<'r, (), ()> {
impl<'r, RX, TX> Eth<'r, RX, TX> { impl<'r, RX, TX> Eth<'r, RX, TX> {
pub fn setup_gem0_clock(tx_clock: u32) { pub fn setup_gem0_clock(tx_clock: u32) {
let io_pll = CpuClocks::get().io; let io_pll = CpuClocks::get().io;
let d0 = (io_pll / tx_clock).min(63); let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).min(63); let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new(); let slcr = slcr::RegisterBlock::new();
slcr.gem0_clk_ctrl.write( slcr.gem0_clk_ctrl.write(
@ -215,8 +215,8 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
pub fn setup_gem1_clock(tx_clock: u32) { pub fn setup_gem1_clock(tx_clock: u32) {
let io_pll = CpuClocks::get().io; let io_pll = CpuClocks::get().io;
let d0 = (io_pll / tx_clock).min(63); let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).min(63); let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new(); let slcr = slcr::RegisterBlock::new();
slcr.gem1_clk_ctrl.write( slcr.gem1_clk_ctrl.write(

2
src/zynq/slcr.rs
View File

@ -376,7 +376,7 @@ register_bits!(gem_clk_ctrl,
divisor, u8, 8, 13); divisor, u8, 8, 13);
register_bits_typed!(gem_clk_ctrl, register_bits_typed!(gem_clk_ctrl,
/// Source to generate the ref clock /// Source to generate the ref clock
srcsel, u8, PllSource, 4, 5); srcsel, u8, PllSource, 4, 6);
register_bit!(gem_clk_ctrl, register_bit!(gem_clk_ctrl,
/// SMC reference clock control /// SMC reference clock control
clkact, 0); clkact, 0);