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6 changed files with 107 additions and 73 deletions

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@ -223,7 +223,7 @@ pub fn main_core0() {
// const CHUNK_SIZE: usize = 65536; // const CHUNK_SIZE: usize = 65536;
// match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await { // match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await {
match stream.send_slice(&tx_data[..]).await { match stream.send_slice(&tx_data[..]).await {
Ok(len) => stats_tx.borrow_mut().1 += tx_data.len(), //CHUNK_SIZE, Ok(_len) => stats_tx.borrow_mut().1 += tx_data.len(), //CHUNK_SIZE,
Err(e) => { Err(e) => {
warn!("tx: {:?}", e); warn!("tx: {:?}", e);
break break

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@ -22,6 +22,17 @@ impl<'a> EEPROM<'a> {
} }
} }
#[cfg(feature = "target_kasli_soc")]
pub fn new(i2c: &'a mut I2c, page_size: u8) -> Self {
EEPROM {
i2c: i2c,
port: 3,
address: 0x57,
page_size: page_size,
count_down: unsafe { crate::timer::GlobalTimer::get() }.countdown()
}
}
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
fn select(&mut self) -> Result<(), &'static str> { fn select(&mut self) -> Result<(), &'static str> {
let mask: u16 = 1 << self.port; let mask: u16 = 1 << self.port;
@ -29,6 +40,14 @@ impl<'a> EEPROM<'a> {
Ok(()) Ok(())
} }
#[cfg(feature = "target_kasli_soc")]
fn select(&mut self) -> Result<(), &'static str> {
let mask: u16 = 1 << self.port;
// tca9548 is compatible with pca9548
self.i2c.pca9548_select(0b1110001, mask as u8)?;
Ok(())
}
/// Random read /// Random read
pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> { pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
self.select()?; self.select()?;

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@ -13,7 +13,7 @@ pub struct I2c {
} }
impl I2c { impl I2c {
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
pub fn i2c0() -> Self { pub fn i2c0() -> Self {
// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51 // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {

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@ -20,6 +20,7 @@ use libregister::{
// //
// Current compatibility: // Current compatibility:
// zc706: GPIO 50, 51 == SCL, SDA // zc706: GPIO 50, 51 == SCL, SDA
// kasli_soc: GPIO 50, 51 == SCL, SDA
pub struct RegisterBlock { pub struct RegisterBlock {
pub gpio_output_mask: &'static mut GPIOOutputMask, pub gpio_output_mask: &'static mut GPIOOutputMask,
@ -39,53 +40,66 @@ impl RegisterBlock {
} }
} }
// MASK_DATA_1_MSW: register!(gpio_output_mask,
// Maskable output data for MIO[53:48] /// MASK_DATA_1_MSW:
register!(gpio_output_mask, GPIOOutputMask, RW, u32); /// Maskable output data for MIO[53:48]
#[cfg(feature = "target_zc706")] GPIOOutputMask, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_at!(GPIOOutputMask, 0xE000A00C, new); register_at!(GPIOOutputMask, 0xE000A00C, new);
// Output for SCL #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")] register_bit!(gpio_output_mask,
register_bit!(gpio_output_mask, scl_o, 2); /// Output for SCL
// Output for SDA scl_o, 2);
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_bit!(gpio_output_mask, sda_o, 3); register_bit!(gpio_output_mask,
// Mask for keeping bits except SCL and SDA unchanged /// Output for SDA
#[cfg(feature = "target_zc706")] sda_o, 3);
register_bits!(gpio_output_mask, mask, u16, 16, 31); #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_bits!(gpio_output_mask,
/// Mask for keeping bits except SCL and SDA unchanged
mask, u16, 16, 31);
// DATA_1_RO: register!(gpio_input,
// Input data for MIO[53:32] /// DATA_1_RO:
register!(gpio_input, GPIOInput, RO, u32); /// Input data for MIO[53:32]
#[cfg(feature = "target_zc706")] GPIOInput, RO, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_at!(GPIOInput, 0xE000A064, new); register_at!(GPIOInput, 0xE000A064, new);
// Input for SCL #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")] register_bit!(gpio_input,
register_bit!(gpio_input, scl, 18); /// Input for SCL
// Input for SDA scl, 18);
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_bit!(gpio_input, sda, 19); register_bit!(gpio_input,
/// Input for SDA
sda, 19);
// DIRM_1: register!(gpio_direction,
// Direction mode for MIO[53:32]; 0/1 = in/out /// DIRM_1:
register!(gpio_direction, GPIODirection, RW, u32); /// Direction mode for MIO[53:32]; 0/1 = in/out
#[cfg(feature = "target_zc706")] GPIODirection, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_at!(GPIODirection, 0xE000A244, new); register_at!(GPIODirection, 0xE000A244, new);
// Direction for SCL #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")] register_bit!(gpio_direction,
register_bit!(gpio_direction, scl, 18); /// Direction for SCL
// Direction for SDA scl, 18);
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_bit!(gpio_direction, sda, 19); register_bit!(gpio_direction,
/// Direction for SDA
sda, 19);
// OEN_1: register!(gpio_output_enable,
// Output enable for MIO[53:32] /// OEN_1:
register!(gpio_output_enable, GPIOOutputEnable, RW, u32); /// Output enable for MIO[53:32]
#[cfg(feature = "target_zc706")] GPIOOutputEnable, RW, u32);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_at!(GPIOOutputEnable, 0xE000A248, new); register_at!(GPIOOutputEnable, 0xE000A248, new);
// Output enable for SCL #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")] register_bit!(gpio_output_enable,
register_bit!(gpio_output_enable, scl, 18); /// Output enable for SCL
// Output enable for SDA scl, 18);
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
register_bit!(gpio_output_enable, sda, 19); register_bit!(gpio_output_enable,
/// Output enable for SDA
sda, 19);

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@ -19,7 +19,7 @@ pub mod gic;
pub mod time; pub mod time;
pub mod timer; pub mod timer;
pub mod sdio; pub mod sdio;
#[cfg(feature = "target_zc706")] #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
pub mod i2c; pub mod i2c;
pub mod logger; pub mod logger;
pub mod ps7_init; pub mod ps7_init;

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@ -30,8 +30,9 @@ pub trait RegisterRW: RegisterR + RegisterW {
#[doc(hidden)] #[doc(hidden)]
#[macro_export] #[macro_export]
macro_rules! register_common { macro_rules! register_common {
($mod_name: ident, $struct_name: ident, $access: ty, $inner: ty) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, $access: ty, $inner: ty) => (
#[repr(C)] #[repr(C)]
$(#[$outer])*
pub struct $struct_name { pub struct $struct_name {
inner: $access, inner: $access,
} }
@ -52,7 +53,7 @@ macro_rules! register_common {
#[macro_export] #[macro_export]
macro_rules! register_r { macro_rules! register_r {
($mod_name: ident, $struct_name: ident) => ( ($mod_name: ident, $struct_name: ident) => (
impl libregister::RegisterR for $struct_name { impl $crate::RegisterR for $struct_name {
type R = $mod_name::Read; type R = $mod_name::Read;
#[inline] #[inline]
@ -67,7 +68,7 @@ macro_rules! register_r {
#[macro_export] #[macro_export]
macro_rules! register_w { macro_rules! register_w {
($mod_name: ident, $struct_name: ident) => ( ($mod_name: ident, $struct_name: ident) => (
impl libregister::RegisterW for $struct_name { impl $crate::RegisterW for $struct_name {
type W = $mod_name::Write; type W = $mod_name::Write;
#[inline] #[inline]
@ -88,7 +89,7 @@ macro_rules! register_w {
#[macro_export] #[macro_export]
macro_rules! register_rw { macro_rules! register_rw {
($mod_name: ident, $struct_name: ident) => ( ($mod_name: ident, $struct_name: ident) => (
impl libregister::RegisterRW for $struct_name { impl $crate::RegisterRW for $struct_name {
#[inline] #[inline]
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) { fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
unsafe { unsafe {
@ -101,7 +102,7 @@ macro_rules! register_rw {
} }
); );
($mod_name: ident, $struct_name: ident, $mask: expr) => ( ($mod_name: ident, $struct_name: ident, $mask: expr) => (
impl libregister::RegisterRW for $struct_name { impl $crate::RegisterRW for $struct_name {
#[inline] #[inline]
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) { fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
unsafe { unsafe {
@ -119,7 +120,7 @@ macro_rules! register_rw {
#[macro_export] #[macro_export]
macro_rules! register_vcell { macro_rules! register_vcell {
($mod_name: ident, $struct_name: ident) => ( ($mod_name: ident, $struct_name: ident) => (
impl libregister::RegisterR for $struct_name { impl $crate::RegisterR for $struct_name {
type R = $mod_name::Read; type R = $mod_name::Read;
#[inline] #[inline]
@ -128,7 +129,7 @@ macro_rules! register_vcell {
$mod_name::Read { inner } $mod_name::Read { inner }
} }
} }
impl libregister::RegisterW for $struct_name { impl $crate::RegisterW for $struct_name {
type W = $mod_name::Write; type W = $mod_name::Write;
#[inline] #[inline]
@ -141,7 +142,7 @@ macro_rules! register_vcell {
self.inner.set(w.inner); self.inner.set(w.inner);
} }
} }
impl libregister::RegisterRW for $struct_name { impl $crate::RegisterRW for $struct_name {
#[inline] #[inline]
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) { fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
let r = self.read(); let r = self.read();
@ -157,37 +158,37 @@ macro_rules! register_vcell {
#[macro_export] #[macro_export]
macro_rules! register { macro_rules! register {
// Define read-only register // Define read-only register
($mod_name: ident, $struct_name: ident, RO, $inner: ty) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, RO, $inner: ty) => (
libregister::register_common!($mod_name, $struct_name, libregister::RO<$inner>, $inner); $crate::register_common!($mod_name, $(#[$outer])* $struct_name, $crate::RO<$inner>, $inner);
libregister::register_r!($mod_name, $struct_name); $crate::register_r!($mod_name, $struct_name);
); );
// Define write-only register // Define write-only register
($mod_name: ident, $struct_name: ident, WO, $inner: ty) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, WO, $inner: ty) => (
libregister::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner); $crate::register_common!($mod_name, $(#[$outer])* $struct_name, volatile_register::WO<$inner>, $inner);
libregister::register_w!($mod_name, $struct_name); $crate::register_w!($mod_name, $struct_name);
); );
// Define read-write register // Define read-write register
($mod_name: ident, $struct_name: ident, RW, $inner: ty) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, RW, $inner: ty) => (
libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner); $crate::register_common!($mod_name, $(#[$outer])* $struct_name, volatile_register::RW<$inner>, $inner);
libregister::register_r!($mod_name, $struct_name); $crate::register_r!($mod_name, $struct_name);
libregister::register_w!($mod_name, $struct_name); $crate::register_w!($mod_name, $struct_name);
libregister::register_rw!($mod_name, $struct_name); $crate::register_rw!($mod_name, $struct_name);
); );
// Define read-write register // Define read-write register
($mod_name: ident, $struct_name: ident, VolatileCell, $inner: ty) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, VolatileCell, $inner: ty) => (
libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner); $crate::register_common!($mod_name, $(#[$outer])* $struct_name, VolatileCell<$inner>, $inner);
libregister::register_vcell!($mod_name, $struct_name); $crate::register_vcell!($mod_name, $struct_name);
); );
// Define read-write register with mask on write (for WTC mixed access.) // Define read-write register with mask on write (for WTC mixed access.)
($mod_name: ident, $struct_name: ident, RW, $inner: ty, $mask: expr) => ( ($mod_name: ident, $(#[$outer:meta])* $struct_name: ident, RW, $inner: ty, $mask: expr) => (
libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner); $crate::register_common!($mod_name, $(#[$outer])* $struct_name, volatile_register::RW<$inner>, $inner);
libregister::register_r!($mod_name, $struct_name); $crate::register_r!($mod_name, $struct_name);
libregister::register_w!($mod_name, $struct_name); $crate::register_w!($mod_name, $struct_name);
libregister::register_rw!($mod_name, $struct_name, $mask); $crate::register_rw!($mod_name, $struct_name, $mask);
); );
} }