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zynq-rs
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14 changed files with 43 additions and 49 deletions
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2
default.nix
View File

@ -36,7 +36,7 @@ let
"${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}" cargoSha256Experiments;
"${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}" cargoSha256SZL;
};
targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
targets = ["zc706" "coraz7" "redpitaya"];
in
{
inherit cargo-xbuild;

1
experiments/Cargo.toml
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@ -9,7 +9,6 @@ edition = "2018"
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
default = ["target_zc706"]
[dependencies]

25
experiments/src/main.rs
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@ -105,20 +105,31 @@ pub fn main_core0() {
.boot_mode_pins()
);
#[cfg(any(
feature = "target_zc706",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
#[cfg(feature = "target_zc706")]
const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_coraz7")]
const CPU_FREQ: u32 = 650_000_000;
#[cfg(feature = "target_redpitaya")]
const CPU_FREQ: u32 = 800_000_000;
info!("Setup clock sources...");
ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart();
#[cfg(feature = "target_zc706")]
{
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart();
}
#[cfg(feature = "target_coraz7")]
{
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart();
}
#[cfg(feature = "target_redpitaya")]
{
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart();
}
info!("PLLs set up");
let clocks = zynq::clocks::Clocks::get();
info!(

1
libboard_zynq/Cargo.toml
View File

@ -9,7 +9,6 @@ edition = "2018"
target_zc706 = []
target_coraz7 = []
target_redpitaya = []
target_kasli_soc = []
ipv6 = [ "smoltcp/proto-ipv6" ]
[dependencies]

2
libboard_zynq/src/clocks/source.rs
View File

@ -8,8 +8,6 @@ pub const PS_CLK: u32 = 33_333_333;
pub const PS_CLK: u32 = 50_000_000;
#[cfg(feature = "target_redpitaya")]
pub const PS_CLK: u32 = 33_333_333;
#[cfg(feature = "target_kasli_soc")]
pub const PS_CLK: u32 = 33_333_333;
/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[

43
libboard_zynq/src/ddr/mod.rs
View File

@ -20,11 +20,8 @@ const DDR_FREQ: u32 = 525_000_000;
/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
const DDR_FREQ: u32 = 533_333_333;
#[cfg(feature = "target_kasli_soc")]
/// MT41K256M16HA-125:E: 800 MHz DDR3L at 533 MHz
const DDR_FREQ: u32 = 533_333_333;
const DCI_MAX_FREQ: u32 = 10_000_000;
/// MT41K256M16HA-125
const DCI_FREQ: u32 = 10_000_000;
pub struct DdrRam {
regs: &'static mut regs::RegisterBlock,
@ -64,7 +61,7 @@ impl DdrRam {
}
fn calculate_dci_divisors(clocks: &Clocks) -> (u8, u8) {
let target = (DCI_MAX_FREQ - 1 + clocks.ddr) / DCI_MAX_FREQ;
let target = (DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ;
let mut best = None;
let mut best_error = 0;
@ -147,13 +144,13 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")]
let data1_config = data0_config.clone();
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
let data0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::VrefDifferential)
.term_en(true)
.dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
let data1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true);
#[cfg(feature = "target_redpitaya")]
@ -176,13 +173,13 @@ impl DdrRam {
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(feature = "target_zc706")]
let diff1_config = diff0_config.clone();
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
let diff0_config = slcr::DdriobConfig::zeroed()
.inp_type(slcr::DdriobInputType::Differential)
.term_en(true)
.dci_type(slcr::DdriobDciType::Termination)
.output_en(slcr::DdriobOutputEn::Obuf);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
let diff1_config = slcr::DdriobConfig::zeroed()
.pullup_en(true);
#[cfg(feature = "target_redpitaya")]
@ -210,7 +207,7 @@ impl DdrRam {
slcr.ddriob_drive_slew_clock.write(0x00F9861C);
}
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
slcr.ddriob_ddr_ctrl.modify(|_, w| w
.vref_int_en(false)
.vref_ext_en_lower(true)
@ -235,7 +232,7 @@ impl DdrRam {
}
fn configure(&mut self) {
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
self.regs.dram_param0.write(
regs::DramParam0::zeroed()
.t_rc(0x1a)
@ -298,11 +295,11 @@ impl DdrRam {
.emr(0x4)
);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
self.regs.phy_configs[2].modify(
|_, w| w.data_slice_in_use(false)
);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
self.regs.phy_configs[3].modify(
|_, w| w.data_slice_in_use(false)
);
@ -354,7 +351,7 @@ impl DdrRam {
.gatelvl_init_ratio(0xee)
);
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
self.regs.reg_64.modify(
|_, w| w
.phy_ctrl_slave_ratio(0x100)
@ -390,7 +387,7 @@ impl DdrRam {
fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
#[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit;
#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
#[cfg(feature = "target_coraz7")]
let width = regs::DataBusWidth::Width16bit;
#[cfg(feature = "target_redpitaya")]
let width = regs::DataBusWidth::Width16bit;
@ -408,11 +405,7 @@ impl DdrRam {
self.regs.dram_addr_map_col.write(0xFFF00000);
self.regs.dram_addr_map_row.write(0x0F666666);
}
#[cfg(any(
feature = "target_coraz7",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
unsafe {
// row/column address bits
self.regs.dram_addr_map_bank.write(0x00000666);
@ -444,11 +437,9 @@ impl DdrRam {
// filtering address map
#[cfg(feature = "target_zc706")]
let megabytes = 1023;
#[cfg(any(
feature = "target_coraz7",
feature = "target_redpitaya",
feature = "target_kasli_soc",
))]
#[cfg(feature = "target_coraz7")]
let megabytes = 512;
#[cfg(feature = "target_redpitaya")]
let megabytes = 512;
megabytes * 1024 * 1024

2
libboard_zynq/src/sdio/mod.rs
View File

@ -117,7 +117,7 @@ impl Sdio {
);
}
// redpitaya card detect pin
#[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
#[cfg(feature = "target_redpitaya")]
{
unsafe {
slcr.sd0_wp_cd_sel.write(46 << 16);

2
libboard_zynq/src/stdio.rs
View File

@ -47,7 +47,7 @@ impl DerefMut for LazyUart {
LazyUart::Uninitialized => {
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
let uart = Uart::uart0(UART_RATE);
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")]
let uart = Uart::uart1(UART_RATE);
*self = LazyUart::Initialized(uart);
self

2
libboard_zynq/src/uart/mod.rs
View File

@ -46,7 +46,7 @@ impl Uart {
self_
}
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
#[cfg(feature = "target_zc706")]
pub fn uart1(baudrate: u32) -> Self {
slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 1 RxD/TxD Signals to MIO Pins

1
libconfig/Cargo.toml
View File

@ -14,5 +14,4 @@ log = "0.4"
target_zc706 = []
target_coraz7 = []
target_redpitaya = []
target_kasli_soc = []
ipv6 = []

4
libconfig/src/net_settings.rs
View File

@ -43,10 +43,6 @@ pub fn get_adresses(cfg: &Config) -> NetAddresses {
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
#[cfg(feature = "target_redpitaya")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
#[cfg(feature = "target_kasli_soc")]
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x56]);
#[cfg(feature = "target_kasli_soc")]
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
hardware_addr = addr;

5
libcortex_a9/Cargo.toml
View File

@ -5,8 +5,11 @@ authors = ["M-Labs"]
edition = "2018"
[features]
target_zc706 = []
target_coraz7 = []
target_redpitaya = []
power_saving = []
default = []
default = ["target_zc706"]
[dependencies]
bit_field = "0.10"

1
libsupport_zynq/Cargo.toml
View File

@ -9,7 +9,6 @@ edition = "2018"
target_zc706 = ["libboard_zynq/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
panic_handler = []
dummy_irq_handler = []
alloc_core = []

1
szl/Cargo.toml
View File

@ -9,7 +9,6 @@ edition = "2018"
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
default = ["target_zc706"]
[dependencies]