libboard_zynq: use log logging

Cargo.lock

@@ -66,6 +66,7 @@ dependencies = [
  "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "libcortex_a9 0.0.0",
  "libregister 0.0.0",
+ "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
  "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -98,7 +99,6 @@ dependencies = [
  "libcortex_a9 0.0.0",
  "libregister 0.0.0",
  "linked_list_allocator 0.8.2 (registry+https://github.com/rust-lang/crates.io-index)",
- "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
  "r0 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
 

experiments/link.x

@@ -65,4 +65,4 @@ SECTIONS
     }
 }
 
-ASSERT(SIZEOF(.stack0) >= 0x8000, "less than 32 KB left for stack");
+ASSERT(SIZEOF(.stack0) >= 0x1000, "less than 4 KB left for stack");

experiments/src/main.rs

@@ -6,7 +6,6 @@ extern crate alloc;
 use core::{mem::transmute, task::Poll};
 use alloc::{borrow::ToOwned, collections::BTreeMap, format};
 use log::info;
-use embedded_hal::timer::CountDown;
 use libregister::RegisterR;
 use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
 use libboard_zynq::{
@@ -17,8 +16,6 @@ use libboard_zynq::{
         wire::{EthernetAddress, IpAddress, IpCidr},
         iface::{NeighborCache, EthernetInterfaceBuilder, Routes},
         time::Instant,
-        socket::SocketSet,
-        socket::{TcpSocket, TcpSocketBuffer},
     },
     time::Milliseconds,
 };
@@ -37,7 +34,7 @@ pub fn main_core0() {
     // zynq::clocks::CpuClocks::enable_io(1_250_000_000);
     println!("\nzc706 main");
 
-    libsupport_zynq::logger::init().unwrap();
+    libboard_zynq::logger::init().unwrap();
     log::set_max_level(log::LevelFilter::Trace);
 
     info!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
@@ -47,7 +44,7 @@ pub fn main_core0() {
     #[cfg(feature = "target_cora_z7_10")]
     const CPU_FREQ: u32 = 650_000_000;
 
-    println!("Setup clock sources...");
+    info!("Setup clock sources...");
     ArmPll::setup(2 * CPU_FREQ);
     Clocks::set_cpu_freq(CPU_FREQ);
     #[cfg(feature = "target_zc706")]
@@ -55,9 +52,9 @@ pub fn main_core0() {
         IoPll::setup(1_000_000_000);
         libboard_zynq::stdio::drop_uart();
     }
-    println!("PLLs set up");
+    info!("PLLs set up");
     let clocks = zynq::clocks::Clocks::get();
-    println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
+    info!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
 
     let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
     let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
@@ -77,6 +74,7 @@ pub fn main_core0() {
     ddr.memtest();
     ram::init_alloc_ddr(&mut ddr);
 
+    #[cfg(dev)]
     for i in 0..=1 {
         let mut flash_io = flash.manual_mode(i);
         // println!("rdcr={:02X}", flash_io.rdcr());
@@ -109,38 +107,12 @@ pub fn main_core0() {
             flash_io.erase(0);
         });
         flash_io.write_enabled(|flash_io| {
-            flash_io.program(0, [0x23054223; (0x100 >> 2)].iter().cloned());
+            flash_io.program(0, [0x23054223; 0x100 >> 2].iter().cloned());
         });
 
         flash = flash_io.stop();
     }
 
-    let (mut tx, mut rx) = sync_channel::sync_channel(0);
-    task::spawn(async move {
-        println!("outer task");
-        while let Some(item) = *rx.async_recv().await {
-            println!("received {}", item);
-        }
-    });
-    task::spawn(async {
-        for i in 1..=3 {
-            println!("outer task2: {}", i);
-            task::r#yield().await;
-        }
-    });
-    task::block_on(async {
-        task::spawn(async {
-            println!("inner task");
-        });
-
-        for i in 1..=10 {
-            println!("yield {}", i);
-            task::r#yield().await;
-            tx.async_send(Some(i)).await;
-        }
-        tx.async_send(None).await;
-    });
-
     let core1 = boot::Core1::start();
 
     let (mut core1_req, rx) = sync_channel(10);
@@ -178,23 +150,13 @@ pub fn main_core0() {
         unsafe { transmute(tx_descs.as_mut_slice()) },
         unsafe { transmute(tx_buffers.as_mut_slice()) },
     );
-    // loop {
-    //     match eth.recv_next() {
-    //         Ok(None) => {},
-    //         Ok(Some(pkt)) => println!("received {} bytes", pkt.len()),
-    //         Err(e) => println!("e: {:?}", e),
-    //     }
-    // }
 
-    println!("iface...");
     let ethernet_addr = EthernetAddress(HWADDR);
     // IP stack
     let local_addr = IpAddress::v4(192, 168, 1, 51);
     let mut ip_addrs = [IpCidr::new(local_addr, 24)];
-    let mut routes_storage = vec![None; 4];
+    let routes = Routes::new(BTreeMap::new());
-    let routes = Routes::new(/*BTreeMap::new()*/ &mut routes_storage[..]);
+    let neighbor_cache = NeighborCache::new(BTreeMap::new());
-    let mut neighbor_storage = vec![None; 256];
-    let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
     let mut iface = EthernetInterfaceBuilder::new(&mut eth)
         .ethernet_addr(ethernet_addr)
         .ip_addrs(&mut ip_addrs[..])
@@ -202,7 +164,7 @@ pub fn main_core0() {
         .neighbor_cache(neighbor_cache)
         .finalize();
 
-    // TODO: compare with ps7_init
+    ps7_init::report_differences();
 
     Sockets::init(32);
     /// `chargen`
@@ -233,20 +195,20 @@ pub fn main_core0() {
             None =>
                 stream.send("I had trouble reading your name.\n".bytes()).await?,
         }
-        stream.flush().await;
+        let _ = stream.flush().await;
         Ok(())
     }
 
-    let mut counter = alloc::rc::Rc::new(core::cell::RefCell::new(0));
+    let counter = alloc::rc::Rc::new(core::cell::RefCell::new(0));
     task::spawn(async move {
-        while let stream = TcpStream::accept(TCP_PORT, 2048, 2408).await.unwrap() {
+        while let Ok(stream) = TcpStream::accept(TCP_PORT, 2048, 2408).await {
             let counter = counter.clone();
             task::spawn(async move {
                 *counter.borrow_mut() += 1;
                 println!("Serving {} connections", *counter.borrow());
                 handle_connection(stream)
                     .await
-                    .map_err(|e| println!("Connection: {:?}", e));
+                    .unwrap_or_else(|e| println!("Connection: {:?}", e));
                 *counter.borrow_mut() -= 1;
                 println!("Now serving {} connections", *counter.borrow());
             });
@@ -261,7 +223,7 @@ pub fn main_core0() {
             let timestamp = timer.get_us();
             let seconds   = timestamp / 1_000_000;
             let micros    = timestamp % 1_000_000;
-            println!("time: {:6}.{:06}s", seconds, micros);
+            info!("time: {:6}.{:06}s", seconds, micros);
         }
     });
 
@@ -282,7 +244,7 @@ pub fn main_core1() {
     while req.is_none() {
         req = CORE1_REQ.lock().take();
     }
-    let mut req = req.unwrap();
+    let req = req.unwrap();
     let mut res = None;
     while res.is_none() {
         res = CORE1_RES.lock().take();

libboard_zynq/Cargo.toml

@@ -15,6 +15,7 @@ bit_field = "0.10"
 embedded-hal = "0.2"
 nb = "0.1"
 void = { version = "1", default-features = false }
+log = "0.4"
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }
 

libboard_zynq/src/clocks/source.rs

@@ -1,3 +1,4 @@
+use log::debug;
 use libregister::{RegisterR, RegisterW, RegisterRW};
 use super::slcr;
 
@@ -48,6 +49,8 @@ pub trait ClockSource {
         u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK
     }
 
+    fn name() -> &'static str;
+
     /// Zynq-7000 AP SoC Technical Reference Manual:
     /// 25.10.4 PLLs
     fn setup(target_freq: u32) {
@@ -58,6 +61,7 @@ pub trait ClockSource {
             .expect("PLL_FDIV_LOCK_PARAM")
             .1.clone();
 
+        debug!("Set {} to {} Hz", Self::name(), target_freq);
         slcr::RegisterBlock::unlocked(|slcr| {
             let (pll_ctrl, pll_cfg, pll_status) = Self::pll_regs(slcr);
 
@@ -108,6 +112,10 @@ impl ClockSource for ArmPll {
     fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
         pll_status.read().arm_pll_lock()
     }
+
+    fn name() -> &'static str {
+        &"ARM_PLL"
+    }
 }
 
 /// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
@@ -130,6 +138,10 @@ impl ClockSource for DdrPll {
     fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
         pll_status.read().ddr_pll_lock()
     }
+
+    fn name() -> &'static str {
+        &"DDR_PLL"
+    }
 }
 
 /// I/O PLL: Recommended clock for I/O peripherals
@@ -153,4 +165,8 @@ impl ClockSource for IoPll {
     fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
         pll_status.read().io_pll_lock()
     }
+
+    fn name() -> &'static str {
+        &"IO_PLL"
+    }
 }

libboard_zynq/src/ddr/mod.rs

@@ -1,4 +1,5 @@
 use libregister::{RegisterR, RegisterW, RegisterRW};
+use log::{error, info};
 use crate::{print, println};
 use super::slcr::{self, DdriobVrefSel};
 use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
@@ -38,11 +39,9 @@ impl DdrRam {
         DdrPll::setup(2 * DDR_FREQ);
 
         let clocks = Clocks::get();
-        println!("Clocks: {:?}", clocks);
-
         let ddr3x_clk_divisor = 2;
         let ddr2x_clk_divisor = 3;
-        println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
+        info!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             slcr.ddr_clk_ctrl.write(
@@ -63,7 +62,7 @@ impl DdrRam {
             .max(1).min(63) as u8;
         let divisor1 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ / u32::from(divisor0))
             .max(1).min(63) as u8;
-        println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
+        info!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             // Step 1.
@@ -226,7 +225,7 @@ impl DdrRam {
         let patterns: &'static [u32] = &[0xffff_ffff, 0x5555_5555, 0xaaaa_aaaa, 0];
         let mut expected = None;
         for (i, pattern) in patterns.iter().enumerate() {
-            println!("memtest phase {} (status: {:?})", i, self.status());
+            info!("memtest phase {} (status: {:?})", i, self.status());
 
             for megabyte in 0..=(slice.len() / (1024 * 1024)) {
                 let start = megabyte * 1024 * 1024 / 4;
@@ -235,7 +234,7 @@ impl DdrRam {
                     expected.map(|expected| {
                         let read: u32 = *b;
                         if read != expected {
-                            println!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
+                            error!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
                         }
                     });
                     *b = *pattern;

libboard_zynq/src/eth/mod.rs

@@ -1,6 +1,6 @@
 use core::ops::{Deref, DerefMut};
+use log::{error, info, warn};
 use libregister::*;
-use crate::println;
 use super::slcr;
 use super::clocks::Clocks;
 
@@ -389,7 +389,7 @@ impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescLis
                 None
             }
             Err(e) => {
-                println!("eth recv error: {:?}", e);
+                error!("eth recv error: {:?}", e);
                 None
             }
         }
@@ -555,7 +555,7 @@ impl<'r> EthInner<'r> {
         if self.link != link {
             match &link {
                 Some(link) => {
-                    println!("eth: got {:?}", link);
+                    info!("eth: got {:?}", link);
 
                     use phy::LinkSpeed::*;
                     let txclock = match link.speed {
@@ -573,7 +573,7 @@ impl<'r> EthInner<'r> {
                     );
                 }
                 None => {
-                    println!("eth: link lost");
+                    warn!("eth: link lost");
                     phy.modify_control(self, |control|
                                        control.set_autoneg_enable(true)
                                        .set_restart_autoneg(true)

libboard_zynq/src/flash/mod.rs

@@ -1,8 +1,9 @@
 //! Quad-SPI Flash Controller
 
-use crate::{print, println};
 use core::marker::PhantomData;
+use log::{error, info, warn};
 use libregister::{RegisterR, RegisterW, RegisterRW};
+use crate::{print, println};
 use super::slcr;
 use super::clocks::source::{IoPll, ClockSource};
 
@@ -422,17 +423,17 @@ impl Flash<Manual> {
         let sr1 = self.wait_while_sr1_zeroed();
 
         if sr1.e_err() {
-            println!("E_ERR");
+            error!("E_ERR");
         } else if sr1.p_err() {
-            println!("P_ERR");
+            error!("P_ERR");
         } else if sr1.wip() {
-            print!("Erase in progress");
+            info!("Erase in progress");
             while self.read_reg::<SR1>().wip() {
                 print!(".");
             }
             println!("");
         } else {
-            println!("erased? sr1={:02X}", sr1.inner);
+            warn!("erased? sr1={:02X}", sr1.inner);
         }
     }
 
@@ -448,17 +449,17 @@ impl Flash<Manual> {
         let sr1 = self.read_reg::<SR1>();
 
         if sr1.e_err() {
-            println!("E_ERR");
+            error!("E_ERR");
         } else if sr1.p_err() {
-            println!("P_ERR");
+            error!("P_ERR");
         } else if sr1.wip() {
-            println!("Program in progress");
+            info!("Program in progress");
             while self.read_reg::<SR1>().wip() {
                 print!(".");
             }
             println!("");
         } else {
-            println!("programmed? sr1={:02X}", sr1.inner);
+            warn!("programmed? sr1={:02X}", sr1.inner);
         }
     }
 

libboard_zynq/src/lib.rs

@@ -17,3 +17,4 @@ pub mod flash;
 pub mod dmac;
 pub mod time;
 pub mod timer;
+pub mod logger;

libboard_zynq/src/logger.rs

@@ -1,6 +1,6 @@
 //! A logger for the `log` crate
 
-use libboard_zynq::{println, stdio, timer::GlobalTimer};
+use crate::{println, stdio, timer::GlobalTimer};
 
 pub static LOGGER: Logger = Logger;
 

libboard_zynq/src/timer/global.rs

@@ -15,7 +15,7 @@ pub struct GlobalTimer {
 impl GlobalTimer {
     /// Get the potentially uninitialized timer
     pub unsafe fn get() -> GlobalTimer {
-        let mut regs = mpcore::RegisterBlock::new();
+        let regs = mpcore::RegisterBlock::new();
         GlobalTimer { regs }
     }
 

libcortex_a9/src/asm.rs

@@ -1,35 +1,35 @@
 /// The classic no-op
 #[inline]
 pub fn nop() {
-    unsafe { asm!("nop" :::: "volatile") }
+    unsafe { llvm_asm!("nop" :::: "volatile") }
 }
 
 /// Wait For Event
 #[inline]
 pub fn wfe() {
-    unsafe { asm!("wfe" :::: "volatile") }
+    unsafe { llvm_asm!("wfe" :::: "volatile") }
 }
 
 /// Send Event
 #[inline]
 pub fn sev() {
-    unsafe { asm!("sev" :::: "volatile") }
+    unsafe { llvm_asm!("sev" :::: "volatile") }
 }
 
 /// Data Memory Barrier
 #[inline]
 pub fn dmb() {
-    unsafe { asm!("dmb" :::: "volatile") }
+    unsafe { llvm_asm!("dmb" :::: "volatile") }
 }
 
 /// Data Synchronization Barrier
 #[inline]
 pub fn dsb() {
-    unsafe { asm!("dsb" :::: "volatile") }
+    unsafe { llvm_asm!("dsb" :::: "volatile") }
 }
 
 /// Instruction Synchronization Barrier
 #[inline]
 pub fn isb() {
-    unsafe { asm!("isb" :::: "volatile") }
+    unsafe { llvm_asm!("isb" :::: "volatile") }
 }

libcortex_a9/src/cache.rs

@@ -2,7 +2,7 @@
 #[inline(always)]
 pub fn tlbiall() {
     unsafe {
-        asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -10,7 +10,7 @@ pub fn tlbiall() {
 #[inline(always)]
 pub fn iciallu() {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
     }
 }
 
@@ -18,7 +18,7 @@ pub fn iciallu() {
 #[inline(always)]
 pub fn bpiall() {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
     }
 }
 
@@ -26,7 +26,7 @@ pub fn bpiall() {
 #[inline(always)]
 pub fn dccsw(setway: u32) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -38,7 +38,7 @@ pub fn dcisw(setway: u32) {
         // also see example code (for DCCISW, but DCISW will be
         // analogous) "Example code for cache maintenance operations"
         // on pages B2-1286 and B2-1287.
-        asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
     }
 }
 
@@ -58,7 +58,7 @@ pub fn dciall() {
 
     // select L1 data cache
     unsafe {
-        asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -101,7 +101,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
 #[inline(always)]
 pub fn dccimvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
     }
 }
 
@@ -122,7 +122,7 @@ pub fn dcci_slice<T>(slice: &mut [T]) {
 #[inline(always)]
 pub fn dccmvac(addr: usize) {
     unsafe {
-        asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
+        llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
     }
 }
 
@@ -148,7 +148,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
 /// affecting more data than intended.
 #[inline(always)]
 pub unsafe fn dcimvac(addr: usize) {
-    asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
+    llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
 }
 
 /// Data cache clean and invalidate for an object.

libcortex_a9/src/lib.rs

@@ -1,5 +1,5 @@
 #![no_std]
-#![feature(asm, global_asm)]
+#![feature(llvm_asm, global_asm)]
 #![feature(never_type)]
 
 extern crate alloc;

libcortex_a9/src/mmu.rs

@@ -94,7 +94,7 @@ impl L1Entry {
 }
 
 const L1_TABLE_SIZE: usize = 4096;
-static mut l1_table: L1Table = L1Table {
+static mut L1_TABLE: L1Table = L1Table {
     table: [L1Entry(0); L1_TABLE_SIZE]
 };
 
@@ -106,7 +106,7 @@ pub struct L1Table {
 impl L1Table {
     pub fn get() -> &'static mut Self {
         unsafe {
-            &mut l1_table
+            &mut L1_TABLE
         }
     }
 

libcortex_a9/src/regs.rs

@@ -11,7 +11,7 @@ macro_rules! def_reg_r {
             #[inline]
             fn read(&self) -> Self::R {
                 let mut value: u32;
-                unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
+                unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
                 value.into()
             }
         }
@@ -26,7 +26,7 @@ macro_rules! def_reg_w {
             #[inline]
             fn write(&mut self, value: Self::W) {
                 let value: u32 = value.into();
-                unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
+                unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
             }
 
             #[inline]

libsupport_zynq/Cargo.toml

@@ -12,7 +12,6 @@ target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
 [dependencies]
 r0 = "1"
 compiler_builtins = "0.1"
-log = "0.4"
 linked_list_allocator = { version = "0.8", default-features = false }
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }

libsupport_zynq/src/lib.rs

@@ -10,5 +10,4 @@ pub extern crate compiler_builtins;
 pub mod boot;
 mod abort;
 mod panic;
-pub mod logger;
 pub mod ram;