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f07a541c99
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eth: model rx/tx state with type parameters
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2019-06-09 20:10:41 +02:00 |
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74bd81f87f
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eth: add safety asserts
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2019-06-09 02:23:37 +02:00 |
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824e91e6cb
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eth: rx/tx desc list, start_rx
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2019-06-09 01:02:10 +02:00 |
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b9ca9324f0
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eth: fix initialization
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2019-06-04 23:48:33 +02:00 |
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b13bf72c17
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eth: begin phy communication
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2019-05-30 02:42:42 +02:00 |
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c0610ad66a
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slcr: init gem* rclk/clk
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2019-05-30 02:26:19 +02:00 |
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d10ffe9eb9
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eth: setup mio_pins, configure net_cfg
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2019-05-25 03:06:39 +02:00 |
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6bf210366a
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regs: properly emit doc_comments
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2019-05-24 23:49:49 +02:00 |
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56c2f1d833
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eth: add net_status, phy_maint registers
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2019-05-24 00:20:59 +02:00 |
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ad77e3dc04
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eth: add net_cfg register
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2019-05-24 00:06:29 +02:00 |
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402b8c9ab1
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eth: no unsafe, note, add qbar register fields
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2019-05-23 23:18:36 +02:00 |
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785e726661
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RegisterW/RegisterRW: required &mut self for safety
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2019-05-23 18:01:18 +02:00 |
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b754581452
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eth: add regs and init
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2019-05-07 19:28:33 +02:00 |
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