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961e2e1dd0
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zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
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2019-11-03 02:23:16 +01:00 |
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6bee1f44f4
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zynq: replace unnecessary slcr::unlocked with new
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2019-10-31 20:48:07 +01:00 |
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5c62716a99
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zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
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2019-10-31 03:15:13 +01:00 |
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c046bbf8a2
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move slcr, clocks, uart, eth into src/zynq/
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2019-10-21 22:19:03 +02:00 |
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