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79a0d72976
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zync_us/slcr: add MIO SLCRs
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2022-11-16 08:54:05 -05:00 |
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2b3045b46c
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zync_us: start defining SLCR blocks
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2022-11-15 16:20:09 -05:00 |
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2c179841be
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zynq_us/uart: same register fields as zynq, just a different location
BDIV_MIN/MAX and CD_MAX are also the same
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2022-11-15 16:14:42 -05:00 |
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508fac66e8
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add crate for ultrascale+ drivers
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2022-11-15 16:05:29 -05:00 |
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