M-Labs
/
zynq-rs
11
0
Fork 15
Code Issues 6 Pull Requests 1 Releases Wiki Activity

WIP update version of Rust 

Signed-off-by: Egor Savkin <es@m-labs.hk>
This commit is contained in:
Egor Savkin 2023-02-01 17:55:54 +08:00
parent 67dbb5932f
commit f887219db1
22 changed files with 129 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
Cargo.lock generated
View File

@ -1,5 +1,7 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "bit_field"
version = "0.10.1"
@ -20,9 +22,9 @@ checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
[[package]]
name = "cc"
version = "1.0.73"
version = "1.0.79"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2fff2a6927b3bb87f9595d67196a70493f627687a71d87a0d692242c33f58c11"
checksum = "50d30906286121d95be3d479533b458f87493b30a4b5f79a607db8f5d11aa91f"
[[package]]
name = "cfg-if"
@ -32,15 +34,14 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
[[package]]
name = "compiler_builtins"
version = "0.1.39"
version = "0.1.85"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
checksum = "13e81c6cd7ab79f51a0c927d22858d61ad12bd0b3865f0b13ece02a4486aeabb"
[[package]]
name = "core_io"
version = "0.1.20210325"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
version = "0.1.20221029"
source = "git+https://github.com/thomasfire/rust-core_io.git#cdaefa2b56c0782364a76945bb3664663fdcfe52"
dependencies = [
"rustc_version",
]
@ -70,9 +71,9 @@ dependencies = [
[[package]]
name = "fatfs"
version = "0.3.5"
version = "0.3.6"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
checksum = "05669f8e7e2d7badc545c513710f0eba09c2fbef683eb859fd79c46c355048e0"
dependencies = [
"bitflags",
"byteorder",
@ -156,9 +157,9 @@ checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
[[package]]
name = "log"
version = "0.4.14"
version = "0.4.17"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
dependencies = [
"cfg-if",
]
@ -198,18 +199,18 @@ checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
[[package]]
name = "rustc_version"
version = "0.1.7"
version = "0.4.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
checksum = "bfa0f585226d2e68097d4f95d113b15b83a82e819ab25717ec0590d9584ef366"
dependencies = [
"semver",
]
[[package]]
name = "semver"
version = "0.1.20"
version = "1.0.16"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
checksum = "58bc9567378fc7690d6b2addae4e60ac2eeea07becb2c64b9f218b53865cba2a"
[[package]]
name = "smoltcp"

3
Cargo.toml
View File

@ -18,3 +18,6 @@ opt-level = 's'
lto = true
debug-assertions = false
overflow-checks = false
[patch.crates-io]
core_io = { git = "https://github.com/thomasfire/rust-core_io.git" }

2
README.md
View File

@ -35,7 +35,7 @@ nix develop
cargo xbuild --release -p experiments
```
Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments`, or `result/experiments.elf` for Nix Flakes build.
Currently the ELF output is placed at `target/armv7-none-eabi/release/experiments`, or `result/experiments.elf` for Nix Flakes build.
## Debug

2
experiments/Cargo.toml
View File

@ -3,7 +3,7 @@ name = "experiments"
description = "Developing bare-metal Rust on Zynq"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]

7
experiments/src/main.rs
View File

@ -1,12 +1,13 @@
#![no_std]
#![no_main]
#![feature(const_in_array_repeat_expressions)]
#![feature(naked_functions)]
#![feature(asm)]
//#![feature(const_in_array_repeat_expressions)]
//#![feature(naked_functions)]
//#![feature(asm)]
extern crate alloc;
use alloc::collections::BTreeMap;
use core::arch::asm;
use libasync::{
delay,
smoltcp::{Sockets, TcpStream},

11
flake.nix
View File

@ -9,8 +9,8 @@
pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
rustManifest = pkgs.fetchurl {
url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
url = "https://static.rust-lang.org/dist/2022-10-29/channel-rust-nightly.toml";
sha256 = "06gj42lrd7967q1fm12wd0nm6l1zckwd38xpprzsjyvfsc60pcw3";
};
rustTargets = [];
rustChannelOfTargets = _channel: _date: targets:
@ -141,15 +141,15 @@
cargo-xbuild = rustPlatform.buildRustPackage rec {
pname = "cargo-xbuild";
version = "0.6.5";
version = "0.6.6";
src = pkgs.fetchFromGitHub {
owner = "rust-osdev";
repo = pname;
rev = "v${version}";
sha256 = "18djvygq9v8rmfchvi2hfj0i6fhn36m716vqndqnj56fiqviwxvf";
sha256 = "sha256-29rCjmzxxIjR5nBN2J3xxP+r8NnPIJV90FkSQQEBbo4=";
};
cargoSha256 = "13sj9j9kl6js75h9xq0yidxy63vixxm9q3f8jil6ymarml5wkhx8";
cargoSha256 = "sha256-tyPhKWDSDNxQy+vpWNS5VP5D8TkUR7MJSAlG8wZsDy4=";
meta = with pkgs.lib; {
description = "Automatically cross-compiles the sysroot crates core, compiler_builtins, and alloc";
@ -281,5 +281,6 @@
(python3.withPackages(ps: [ ps.pyftdi ]))
mkbootimage ];
};
RUST_SRC_PATH = rustPlatform.rustLibSrc;
};
}

2
libasync/Cargo.toml
View File

@ -3,7 +3,7 @@ name = "libasync"
description = "low-level async support"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[dependencies]
#futures = { version = "0.3", default-features = false }

2
libboard_zynq/Cargo.toml
View File

@ -3,7 +3,7 @@ name = "libboard_zynq"
description = "Drivers for peripherals in the Zynq PS"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[features]
target_zc706 = []

4
libconfig/Cargo.toml
View File

@ -2,11 +2,11 @@
name = "libconfig"
version = "0.1.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[dependencies]
libboard_zynq = { path = "../libboard_zynq" }
core_io = { version = "0.1", features = ["collections"] }
core_io = { version = "0.1.20221029", features = ["collections"], git = "https://github.com/thomasfire/rust-core_io.git" }
fatfs = { version = "0.3", features = ["core_io"], default-features = false }
log = "0.4"

2
libcortex_a9/Cargo.toml
View File

@ -2,7 +2,7 @@
name = "libcortex_a9"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[features]
power_saving = []

32
libcortex_a9/src/asm.rs
View File

@ -1,53 +1,55 @@
use core::arch::asm;
/// The classic no-op
#[inline]
pub fn nop() {
unsafe { llvm_asm!("nop" :::: "volatile") }
unsafe { asm!("nop", options(nomem, nostack)) }
}
/// Wait For Event
#[inline]
pub fn wfe() {
unsafe { llvm_asm!("wfe" :::: "volatile") }
unsafe { asm!("wfe", options(nomem, nostack)) }
}
/// Send Event
#[inline]
pub fn sev() {
unsafe { llvm_asm!("sev" :::: "volatile") }
unsafe { asm!("sev", options(nomem, nostack)) }
}
/// Data Memory Barrier
#[inline]
pub fn dmb() {
unsafe { llvm_asm!("dmb" :::: "volatile") }
unsafe { asm!("dmb", options(nomem, nostack)) }
}
/// Data Synchronization Barrier
#[inline]
pub fn dsb() {
unsafe { llvm_asm!("dsb" :::: "volatile") }
unsafe { asm!("dsb", options(nomem, nostack)) }
}
/// Instruction Synchronization Barrier
#[inline]
pub fn isb() {
unsafe { llvm_asm!("isb" :::: "volatile") }
unsafe { asm!("isb", options(nomem, nostack)) }
}
/// Enable IRQ
#[inline]
pub unsafe fn enable_irq() {
llvm_asm!("cpsie i":::: "volatile");
asm!("cpsie i", options(nomem, nostack));
}
/// Disable IRQ, return if IRQ was originally enabled.
#[inline]
pub unsafe fn enter_critical() -> bool {
let mut cpsr: u32;
llvm_asm!(
"mrs $0, cpsr
asm!(
"mrs {}, cpsr
cpsid i"
: "=r"(cpsr) ::: "volatile");
, out(reg) cpsr, options(nomem, nostack));
(cpsr & (1 << 7)) == 0
}
@ -59,18 +61,18 @@ pub unsafe fn exit_critical(enable: bool) {
} else {
0
};
llvm_asm!(
asm!(
"mrs r1, cpsr
bic r1, r1, $0
bic r1, r1, {}
msr cpsr_c, r1"
:: "r"(mask) : "r1");
, in(reg) mask, options(nomem, nostack));
}
/// Exiting IRQ
#[inline]
pub unsafe fn exit_irq() {
llvm_asm!("
asm!("
mrs r0, SPSR
msr CPSR, r0
" ::: "r0");
", options(nomem, nostack));
}

23
libcortex_a9/src/cache.rs
View File

@ -1,11 +1,12 @@
use super::asm::{dmb, dsb};
use super::l2c::*;
use core::arch::asm;
/// Invalidate TLBs
#[inline(always)]
pub fn tlbiall() {
unsafe {
llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0, options(nomem, nostack));
}
}
@ -13,7 +14,7 @@ pub fn tlbiall() {
#[inline(always)]
pub fn iciallu() {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0, options(nomem, nostack));
}
}
@ -21,7 +22,7 @@ pub fn iciallu() {
#[inline(always)]
pub fn bpiall() {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0, options(nomem, nostack));
}
}
@ -29,7 +30,7 @@ pub fn bpiall() {
#[inline(always)]
pub fn dccsw(setway: u32) {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway, options(nomem, nostack));
}
}
@ -41,7 +42,7 @@ pub fn dcisw(setway: u32) {
// also see example code (for DCCISW, but DCISW will be
// analogous) "Example code for cache maintenance operations"
// on pages B2-1286 and B2-1287.
llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway, options(nomem, nostack));
}
}
@ -49,7 +50,7 @@ pub fn dcisw(setway: u32) {
#[inline(always)]
pub fn dccisw(setway: u32) {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway, options(nomem, nostack));
}
}
@ -69,7 +70,7 @@ pub fn dciall_l1() {
// select L1 data cache
unsafe {
llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0, options(nomem, nostack));
}
// Invalidate entire D-Cache by iterating every set and every way
@ -104,7 +105,7 @@ pub fn dcciall_l1() {
// select L1 data cache
unsafe {
llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0, options(nomem, nostack));
}
// Invalidate entire D-Cache by iterating every set and every way
@ -156,7 +157,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
#[inline(always)]
pub fn dccimvac(addr: usize) {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr, options(nomem, nostack));
}
}
@ -198,7 +199,7 @@ pub fn dcci_slice<T>(slice: &[T]) {
#[inline(always)]
pub fn dccmvac(addr: usize) {
unsafe {
llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr, options(nomem, nostack));
}
}
@ -239,7 +240,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
/// affecting more data than intended.
#[inline(always)]
pub unsafe fn dcimvac(addr: usize) {
llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr, options(nomem, nostack));
}
/// Data cache clean and invalidate for an object.

6
libcortex_a9/src/fpu.rs
View File

@ -1,7 +1,9 @@
use core::arch::asm;
/// Enable FPU in the current core.
pub fn enable_fpu() {
unsafe {
llvm_asm!("
asm!("
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, (0b1111<<20)
mcr p15, 0, r1, c1, c0, 2
@ -9,6 +11,6 @@ pub fn enable_fpu() {
vmrs r1, fpexc
orr r1, r1, (1<<30)
vmsr fpexc, r1
":::"r1");
", options(nomem, nostack));
}
}

9
libcortex_a9/src/lib.rs
View File

@ -1,7 +1,6 @@
#![no_std]
#![feature(llvm_asm, global_asm)]
#![feature(never_type)]
#![feature(const_fn)]
//#![feature(const_fn)]
extern crate alloc;
@ -17,6 +16,7 @@ pub mod sync_channel;
mod uncached;
pub use fpu::enable_fpu;
pub use uncached::UncachedSlice;
use core::arch::{global_asm, asm};
global_asm!(include_str!("exceptions.s"));
@ -50,8 +50,7 @@ macro_rules! interrupt_handler {
($name:ident, $name2:ident, $stack0:ident, $stack1:ident, $body:block) => {
#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn $name() -> ! {
pub unsafe extern "C" fn $name() {
asm!(
// setup SP, depending on CPU 0 or 1
"mrc p15, #0, r0, c0, c0, #5",
@ -67,6 +66,6 @@ macro_rules! interrupt_handler {
}
#[no_mangle]
pub unsafe extern "C" fn $name2() -> ! $body
pub unsafe extern "C" fn $name2() $body
};
}

51
libcortex_a9/src/regs.rs
View File

@ -2,6 +2,7 @@ use libregister::{
register_bit, register_bits,
RegisterR, RegisterW, RegisterRW,
};
use core::arch::asm;
macro_rules! def_reg_r {
($name:tt, $type: ty, $asm_instr:tt) => {
@ -11,7 +12,7 @@ macro_rules! def_reg_r {
#[inline]
fn read(&self) -> Self::R {
let mut value: u32;
unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
unsafe { asm!($asm_instr, out(reg) value, options(nomem, nostack)) }
value.into()
}
}
@ -26,7 +27,7 @@ macro_rules! def_reg_w {
#[inline]
fn write(&mut self, value: Self::W) {
let value: u32 = value.into();
unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
unsafe { asm!($asm_instr, in(reg) value, options(nomem, nostack)) }
}
#[inline]
@ -71,29 +72,29 @@ macro_rules! wrap_reg {
/// Stack Pointer
pub struct SP;
def_reg_r!(SP, u32, "mov $0, sp");
def_reg_w!(SP, u32, "mov sp, $0");
def_reg_r!(SP, u32, "mov {}, sp");
def_reg_w!(SP, u32, "mov sp, {}");
/// Link register (function call return address)
pub struct LR;
def_reg_r!(LR, u32, "mov $0, lr");
def_reg_w!(LR, u32, "mov lr, $0");
def_reg_r!(LR, u32, "mov {}, lr");
def_reg_w!(LR, u32, "mov lr, {}");
pub struct VBAR;
def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");
pub struct MVBAR;
def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");
pub struct HVBAR;
def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");
/// Multiprocess Affinity Register
pub struct MPIDR;
def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
wrap_reg!(mpidr);
register_bits!(mpidr,
/// CPU core index
@ -106,15 +107,15 @@ register_bit!(mpidr,
u, 30);
pub struct DFAR;
def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");
pub struct DFSR;
def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");
pub struct SCTLR;
wrap_reg!(sctlr);
def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
register_bit!(sctlr,
/// Enables MMU
m, 0);
@ -147,8 +148,8 @@ register_bit!(sctlr,
/// Auxiliary Control Register
pub struct ACTLR;
wrap_reg!(actlr);
def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
// SMP bit
register_bit!(actlr, parity_on, 9);
register_bit!(actlr, alloc_one_way, 8);
@ -183,17 +184,17 @@ impl ACTLR {
/// Domain Access Control Register
pub struct DACR;
def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");
/// Translation Table Base Register 0
pub struct TTBR0;
/// Translation Table Base Register 1
pub struct TTBR1;
def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
wrap_reg!(ttbr);
register_bits!(ttbr, table_base, u32, 14, 31);
register_bit!(ttbr, irgn0, 6);

22
libcortex_a9/src/sync_channel.rs
View File

@ -170,15 +170,35 @@ impl<'a, T> Iterator for Receiver<'a, T> where T: Clone {
}
}
macro_rules! count_tts {
() => {};
($_head:tt $($tail:tt)*) => {1usize + count_tts!($($tail)*)};
}
const fn count_helper<const N: usize>(_: [(); N]) -> usize { N }
#[macro_export]
/// Macro for initializing the sync_channel with static buffer and indexes.
/// Note that this requires `#![feature(const_in_array_repeat_expressions)]`
macro_rules! sync_channel {
($t: ty, $cap: expr) => {
{
// TODO remove const_in_array_repeat_expressions
use core::sync::atomic::{AtomicUsize, AtomicPtr};
use core::mem::MaybeUninit;
use $crate::sync_channel::{Sender, Receiver};
static LIST: [AtomicPtr<$t>; $cap + 1] = [AtomicPtr::new(core::ptr::null_mut()); $cap + 1];
static LIST: [AtomicPtr<$t>; $cap + 1] = [
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut()),
AtomicPtr::new(core::ptr::null_mut())];
static WRITE: AtomicUsize = AtomicUsize::new(0);
static READ: AtomicUsize = AtomicUsize::new(0);
(Sender::new(&LIST, &WRITE, &READ), Receiver::new(&LIST, &WRITE, &READ))

2
libregister/Cargo.toml
View File

@ -2,7 +2,7 @@
name = "libregister"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[dependencies]
vcell = "0.1"

4
libsupport_zynq/Cargo.toml
View File

@ -3,7 +3,7 @@ name = "libsupport_zynq"
description = "Software support for running in the Zynq PS"
version = "0.0.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[features]
target_zc706 = ["libboard_zynq/target_zc706"]
@ -18,7 +18,7 @@ default = ["panic_handler", "dummy_irq_handler"]
[dependencies]
r0 = "1"
compiler_builtins = "=0.1.39"
compiler_builtins = "=0.1.85"
linked_list_allocator = { version = "0.8", default-features = false, features = ["const_mut_refs"] }
libregister = { path = "../libregister" }
libcortex_a9 = { path = "../libcortex_a9" }

1
libsupport_zynq/src/abort.rs
View File

@ -1,6 +1,7 @@
use libregister::RegisterR;
use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler};
use libboard_zynq::{println, stdio};
use core::arch::asm;
interrupt_handler!(UndefinedInstruction, undefined_instruction, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart();

1
libsupport_zynq/src/boot.rs
View File

@ -6,6 +6,7 @@ use libregister::{
};
use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu, interrupt_handler};
use libboard_zynq::{slcr, mpcore};
use core::arch::asm;
extern "C" {
static mut __bss_start: u32;

4
libsupport_zynq/src/lib.rs
View File

@ -2,8 +2,8 @@
#![feature(alloc_error_handler)]
#![feature(panic_info_message)]
#![feature(naked_functions)]
#![feature(asm)]
//#![feature(naked_functions)]
//#![feature(asm)]
pub extern crate alloc;
pub extern crate compiler_builtins;

4
szl/Cargo.toml
View File

@ -3,7 +3,7 @@ name = "szl"
description = "Simple Zynq Loader"
version = "0.1.0"
authors = ["M-Labs"]
edition = "2018"
edition = "2021"
[features]
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
@ -15,7 +15,7 @@ default = ["target_zc706"]
[dependencies]
log = "0.4"
byteorder = { version = "1.3", default-features = false }
core_io = { version = "0.1", features = ["collections"] }
core_io = { version = "0.1.20221029", features = ["collections"], git = "https://github.com/thomasfire/rust-core_io.git" }
libboard_zynq = { path = "../libboard_zynq" }
libsupport_zynq = { path = "../libsupport_zynq" }