mmu: add early memory barrier to L1Table.update()

pull/42/head
Astro 2020-06-18 00:46:34 +02:00
parent 7c4d390ce4
commit f50018092c
1 changed files with 1 additions and 0 deletions

View File

@ -368,6 +368,7 @@ impl L1Table {
let result = f(&mut section);
entry.set_section(section);
asm::dmb();
cache::tlbiall();
asm::dsb();
asm::isb();