M-Labs/zynq-rs
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ddr: delint

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Astro 2020-07-06 19:46:18 +02:00
parent f68b5896ce
commit e4e7141bf3
1 changed files with 1 additions and 1 deletions
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2
libboard_zynq/src/ddr/mod.rs
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@ -316,7 +316,7 @@ impl DdrRam {
for megabyte in 0..slice.len() / (1024 * 1024) {
let start = megabyte * 1024 * 1024 / 4;
let end = ((megabyte + 1) * 1024 * 1024 / 4);
let end = (megabyte + 1) * 1024 * 1024 / 4;
for b in slice[start..end].iter_mut() {
expected.map(|expected| {
let read: u32 = *b;