M-Labs/zynq-rs
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zynq::flash: add rdsr1()

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Astro 2019-12-12 01:02:09 +01:00
parent 3b3b5dc7c1
commit e1068af948
1 changed files with 10 additions and 0 deletions
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10
src/zynq/flash/mod.rs
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@ -14,6 +14,8 @@ const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
/// Instruction: Read Configure Register /// Instruction: Read Configure Register
const INST_RDCR: u8 = 0x35; const INST_RDCR: u8 = 0x35;
/// Instruction: Read Status Register-1
const INST_RDSR1: u8 = 0x05;
/// Instruction: Read Identification /// Instruction: Read Identification
const INST_RDID: u8 = 0x9F; const INST_RDID: u8 = 0x9F;
@ -355,6 +357,14 @@ impl Flash<Manual> {
.next().unwrap() as u8 .next().unwrap() as u8
} }
/// Read Status Register-1
pub fn rdsr1(&mut self) -> u8 {
let args = Some(INST_RDSR1 as u8);
self.transfer(args.into_iter(), 2)
.bytes_transfer().skip(1)
.next().unwrap()
}
/// Read Identifiaction /// Read Identifiaction
pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> { pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>, u32>>> {
let args = Some((INST_RDID as u32) << 24); let args = Some((INST_RDID as u32) << 24);