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zynq-rs
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eth: fix mio_pin setup

This commit is contained in:
Astro 2019-06-29 00:00:22 +02:00
parent 9ab40daca2
commit d6b2321fee
1 changed files with 8 additions and 0 deletions
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8
src/eth/mod.rs
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@ -39,6 +39,7 @@ impl Eth<(), ()> {
slcr.mio_pin_16.write( slcr.mio_pin_16.write(
slcr::MioPin16::zeroed() slcr::MioPin16::zeroed()
.l0_sel(true) .l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)
@ -47,6 +48,7 @@ impl Eth<(), ()> {
slcr.mio_pin_21.write( slcr.mio_pin_21.write(
slcr::MioPin21::zeroed() slcr::MioPin21::zeroed()
.l0_sel(true) .l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)
@ -55,6 +57,7 @@ impl Eth<(), ()> {
slcr.mio_pin_20.write( slcr.mio_pin_20.write(
slcr::MioPin20::zeroed() slcr::MioPin20::zeroed()
.l0_sel(true) .l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)
@ -62,6 +65,8 @@ impl Eth<(), ()> {
// TXD2 // TXD2
slcr.mio_pin_19.write( slcr.mio_pin_19.write(
slcr::MioPin19::zeroed() slcr::MioPin19::zeroed()
.l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)
@ -69,6 +74,8 @@ impl Eth<(), ()> {
// TXD1 // TXD1
slcr.mio_pin_18.write( slcr.mio_pin_18.write(
slcr::MioPin18::zeroed() slcr::MioPin18::zeroed()
.l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)
@ -77,6 +84,7 @@ impl Eth<(), ()> {
slcr.mio_pin_17.write( slcr.mio_pin_17.write(
slcr::MioPin17::zeroed() slcr::MioPin17::zeroed()
.l0_sel(true) .l0_sel(true)
.speed(true)
.io_type(slcr::IoBufferType::Hstl) .io_type(slcr::IoBufferType::Hstl)
.pullup(true) .pullup(true)
.disable_rcvr(true) .disable_rcvr(true)