M-Labs
/
zynq-rs
11
0
Fork 15
Code Issues 6 Pull Requests 1 Releases Wiki Activity

Revert "zynq: replace unnecessary slcr::unlocked with new" 

This reverts commit 6bee1f44f4.
This commit is contained in:
Astro 2019-11-06 22:59:17 +01:00
parent eb56dda44f
commit d2df5652d0
4 changed files with 320 additions and 309 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/zynq/clocks.rs
View File

@ -99,29 +99,30 @@ impl CpuClocks {
.nth(0) .nth(0)
.expect("PLL_FDIV_LOCK_PARAM") .expect("PLL_FDIV_LOCK_PARAM")
.1.clone(); .1.clone();
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|regs| {
slcr.ddr_pll_ctrl.modify(|_, w| w regs.ddr_pll_ctrl.modify(|_, w| w
.pll_pwrdwn(false) .pll_pwrdwn(false)
.pll_bypass_force(true) .pll_bypass_force(true)
.pll_fdiv(fdiv) .pll_fdiv(fdiv)
); );
slcr.ddr_pll_cfg.write( regs.ddr_pll_cfg.write(
slcr::PllCfg::zeroed() slcr::PllCfg::zeroed()
.pll_res(pll_res) .pll_res(pll_res)
.pll_cp(pll_cp) .pll_cp(pll_cp)
.lock_cnt(lock_cnt) .lock_cnt(lock_cnt)
); );
slcr.ddr_pll_ctrl.modify(|_, w| w regs.ddr_pll_ctrl.modify(|_, w| w
.pll_reset(true) .pll_reset(true)
); );
slcr.ddr_pll_ctrl.modify(|_, w| w regs.ddr_pll_ctrl.modify(|_, w| w
.pll_reset(false) .pll_reset(false)
); );
while ! slcr.pll_status.read().ddr_pll_lock() {} while ! regs.pll_status.read().ddr_pll_lock() {}
slcr.ddr_pll_ctrl.modify(|_, w| w regs.ddr_pll_ctrl.modify(|_, w| w
.pll_bypass_force(false) .pll_bypass_force(false)
.pll_bypass_qual(false) .pll_bypass_qual(false)
); );
});
} }
} }

9
src/zynq/ddr/mod.rs
View File

@ -42,7 +42,7 @@ impl DdrRam {
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
slcr.ddr_clk_ctrl.write( slcr.ddr_clk_ctrl.write(
slcr::DdrClkCtrl::zeroed() slcr::DdrClkCtrl::zeroed()
.ddr_2xclkact(true) .ddr_2xclkact(true)
@ -50,6 +50,7 @@ impl DdrRam {
.ddr_2xclk_divisor(ddr2x_clk_divisor) .ddr_2xclk_divisor(ddr2x_clk_divisor)
.ddr_3xclk_divisor(ddr3x_clk_divisor) .ddr_3xclk_divisor(ddr3x_clk_divisor)
); );
});
clocks clocks
} }
@ -61,7 +62,7 @@ impl DdrRam {
let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0)) let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
.max(1).min(63) as u8; .max(1).min(63) as u8;
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
// Step 1. // Step 1.
slcr.dci_clk_ctrl.write( slcr.dci_clk_ctrl.write(
slcr::DciClkCtrl::zeroed() slcr::DciClkCtrl::zeroed()
@ -95,12 +96,13 @@ impl DdrRam {
); );
// Step 2.e. // Step 2.e.
while ! slcr.ddriob_dci_status.read().done() {} while ! slcr.ddriob_dci_status.read().done() {}
});
} }
/// Zynq-7000 AP SoC Technical Reference Manual: /// Zynq-7000 AP SoC Technical Reference Manual:
/// 10.6.3 DDR IOB Configuration /// 10.6.3 DDR IOB Configuration
fn configure_iob() { fn configure_iob() {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
let addr_config = slcr::DdriobConfig::zeroed() let addr_config = slcr::DdriobConfig::zeroed()
.output_en(slcr::DdriobOutputEn::Obuf); .output_en(slcr::DdriobOutputEn::Obuf);
slcr.ddriob_addr0.write(addr_config.clone()); slcr.ddriob_addr0.write(addr_config.clone());
@ -154,6 +156,7 @@ impl DdrRam {
.vref_sel(vref_sel) .vref_sel(vref_sel)
.vref_int_en(false) .vref_int_en(false)
); );
});
} }
/// Reset DDR controller /// Reset DDR controller

9
src/zynq/eth/mod.rs
View File

@ -27,7 +27,7 @@ pub struct Eth<'r, RX, TX> {
impl<'r> Eth<'r, (), ()> { impl<'r> Eth<'r, (), ()> {
pub fn default(macaddr: [u8; 6]) -> Self { pub fn default(macaddr: [u8; 6]) -> Self {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
// Manual example: 0x0000_1280 // Manual example: 0x0000_1280
// MDIO // MDIO
slcr.mio_pin_53.write( slcr.mio_pin_53.write(
@ -152,6 +152,7 @@ impl<'r> Eth<'r, (), ()> {
slcr::GpiobCtrl::zeroed() slcr::GpiobCtrl::zeroed()
.vref_en(true) .vref_en(true)
); );
});
Self::gem0(macaddr) Self::gem0(macaddr)
} }
@ -197,7 +198,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63); let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).max(1).min(63); let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
slcr.gem0_clk_ctrl.write( slcr.gem0_clk_ctrl.write(
// 0x0050_0801: 8, 5: 100 Mb/s // 0x0050_0801: 8, 5: 100 Mb/s
// ...: 8, 1: 1000 Mb/s // ...: 8, 1: 1000 Mb/s
@ -213,6 +214,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
slcr::RclkCtrl::zeroed() slcr::RclkCtrl::zeroed()
.clkact(true) .clkact(true)
); );
});
} }
pub fn setup_gem1_clock(tx_clock: u32) { pub fn setup_gem1_clock(tx_clock: u32) {
@ -220,7 +222,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63); let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).max(1).min(63); let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
slcr.gem1_clk_ctrl.write( slcr.gem1_clk_ctrl.write(
slcr::GemClkCtrl::zeroed() slcr::GemClkCtrl::zeroed()
.clkact(true) .clkact(true)
@ -234,6 +236,7 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
slcr::RclkCtrl::zeroed() slcr::RclkCtrl::zeroed()
.clkact(true) .clkact(true)
); );
});
} }
pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> { pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<'r, rx::DescList<'rx>, TX> {

12
src/zynq/uart/mod.rs
View File

@ -14,7 +14,7 @@ pub struct Uart {
impl Uart { impl Uart {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
pub fn serial(baudrate: u32) -> Self { pub fn serial(baudrate: u32) -> Self {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 1 RxD/TxD Signals to MIO Pins // Route UART 1 RxD/TxD Signals to MIO Pins
// TX pin // TX pin
slcr.mio_pin_48.write( slcr.mio_pin_48.write(
@ -31,12 +31,13 @@ impl Uart {
.io_type(slcr::IoBufferType::Lvcmos18) .io_type(slcr::IoBufferType::Lvcmos18)
.pullup(true) .pullup(true)
); );
});
Self::uart1(baudrate) Self::uart1(baudrate)
} }
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_cora_z7_10")]
pub fn serial(baudrate: u32) -> Self { pub fn serial(baudrate: u32) -> Self {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
// Route UART 0 RxD/TxD Signals to MIO Pins // Route UART 0 RxD/TxD Signals to MIO Pins
// TX pin // TX pin
slcr.mio_pin_15.write( slcr.mio_pin_15.write(
@ -53,14 +54,16 @@ impl Uart {
.io_type(slcr::IoBufferType::Lvcmos33) .io_type(slcr::IoBufferType::Lvcmos33)
.pullup(true) .pullup(true)
); );
});
Self::uart0(baudrate) Self::uart0(baudrate)
} }
pub fn uart0(baudrate: u32) -> Self { pub fn uart0(baudrate: u32) -> Self {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
slcr.uart_rst_ctrl.reset_uart0(); slcr.uart_rst_ctrl.reset_uart0();
slcr.aper_clk_ctrl.enable_uart0(); slcr.aper_clk_ctrl.enable_uart0();
slcr.uart_clk_ctrl.enable_uart0(); slcr.uart_clk_ctrl.enable_uart0();
});
let mut self_ = Uart { let mut self_ = Uart {
regs: regs::RegisterBlock::uart0(), regs: regs::RegisterBlock::uart0(),
}; };
@ -69,10 +72,11 @@ impl Uart {
} }
pub fn uart1(baudrate: u32) -> Self { pub fn uart1(baudrate: u32) -> Self {
let slcr = slcr::RegisterBlock::new(); slcr::RegisterBlock::unlocked(|slcr| {
slcr.uart_rst_ctrl.reset_uart1(); slcr.uart_rst_ctrl.reset_uart1();
slcr.aper_clk_ctrl.enable_uart1(); slcr.aper_clk_ctrl.enable_uart1();
slcr.uart_clk_ctrl.enable_uart1(); slcr.uart_clk_ctrl.enable_uart1();
});
let mut self_ = Uart { let mut self_ = Uart {
regs: regs::RegisterBlock::uart1(), regs: regs::RegisterBlock::uart1(),
}; };