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split into lib{register, cortex_a9, board_zynq, board_zc706} crates

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This commit is contained in:
Astro 2019-12-17 23:35:58 +01:00
parent 1036ecc0f7
commit cf1983e543
47 changed files with 218 additions and 105 deletions
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59
Cargo.lock generated
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@ -15,6 +15,53 @@ name = "byteorder"
version = "1.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]]
name = "libboard_zc706"
version = "0.0.0"
dependencies = [
"libboard_zynq 0.0.0",
"libcortex_a9 0.0.0",
"libregister 0.0.0",
"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
]
[[package]]
name = "libboard_zynq"
version = "0.0.0"
dependencies = [
"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
"libcortex_a9 0.0.0",
"libregister 0.0.0",
"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]]
name = "libcortex_a9"
version = "0.0.0"
dependencies = [
"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
"libregister 0.0.0",
"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]]
name = "libregister"
version = "0.0.0"
dependencies = [
"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]]
name = "linked_list_allocator"
version = "0.6.4"
@ -53,18 +100,6 @@ dependencies = [
"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]]
name = "zc706"
version = "0.0.0"
dependencies = [
"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
]
[metadata]
"checksum bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"
"checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd"

25
Cargo.toml
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@ -1,8 +1,5 @@
[package]
name = "zc706"
version = "0.0.0"
authors = ["Astro <astro@spaceboyz.net>"]
edition = "2018"
[workspace]
members = ["libregister", "libcortex_a9", "libboard_zynq", "libboard_zc706"]
[profile.dev]
panic = "abort"
@ -13,21 +10,3 @@ panic = "abort"
debug = true
lto = true # Link-Time Optimization
opt-level = 'z' # Optimize for size.
[features]
target_zc706 = []
target_cora_z7_10 = []
default = ["target_zc706"]
[dependencies]
r0 = "0.2"
vcell = "0.1"
volatile-register = "0.2"
bit_field = "0.10"
linked_list_allocator = { version = "0.6", default-features = false }
[dependencies.smoltcp]
git = "https://github.com/m-labs/smoltcp.git"
rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
features = ["ethernet", "proto-ipv4", "socket-tcp"]
default-features = false

2
default.nix
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@ -43,7 +43,7 @@ let
zc706 = xbuildRustPackage {
name = "zc706";
src = ./.;
cargoSha256 = "1k7b0bzkzhqggrmgzs7md7rrbid0b59a5l96ppr4rwxnh841vcdk";
cargoSha256 = "15icqy72dck82czpsqz41yjsdar17vpi15v22j6z0zxhzf517rf7";
nativeBuildInputs = [
gcc
];

23
libboard_zc706/Cargo.toml Normal file
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@ -0,0 +1,23 @@
[package]
name = "libboard_zc706"
version = "0.0.0"
authors = ["Astro <astro@spaceboyz.net>"]
edition = "2018"
[features]
target_zc706 = []
target_cora_z7_10 = []
default = ["target_zc706"]
[dependencies]
r0 = "0.2"
linked_list_allocator = { version = "0.6", default-features = false }
libregister = { path = "../libregister" }
libcortex_a9 = { path = "../libcortex_a9" }
libboard_zynq = { path = "../libboard_zynq" }
[dependencies.smoltcp]
git = "https://github.com/m-labs/smoltcp.git"
rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
features = ["ethernet", "proto-ipv4", "socket-tcp"]
default-features = false

2
src/abort.rs → libboard_zc706/src/abort.rs
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@ -1,4 +1,4 @@
use crate::println;
use libboard_zynq::println;
#[no_mangle]
pub unsafe extern "C" fn PrefetchAbort() {

12
src/boot.rs → libboard_zc706/src/boot.rs
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@ -1,8 +1,10 @@
use r0::zero_bss;
use vcell::VolatileCell;
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use crate::cortex_a9::{asm, regs::*, cache, mmu};
use crate::zynq::{slcr, mpcore};
use libregister::{
VolatileCell,
RegisterR, RegisterW, RegisterRW,
};
use libcortex_a9::{asm, regs::*, cache, mmu};
use libboard_zynq::{slcr, mpcore};
extern "C" {
static mut __bss_start: u32;
@ -81,7 +83,7 @@ unsafe fn boot_core1() -> ! {
}
fn l1_cache_init() {
use crate::cortex_a9::cache::*;
use libcortex_a9::cache::*;
// Invalidate TLBs
tlbiall();

18
src/main.rs → libboard_zc706/src/main.rs
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@ -1,9 +1,6 @@
#![no_std]
#![no_main]
#![feature(asm)]
#![feature(global_asm)]
#![feature(naked_functions)]
#![feature(never_type)]
#![feature(alloc_error_handler)]
#![feature(panic_info_message)]
// TODO: disallow unused/dead_code when code moves into a lib crate
@ -18,16 +15,13 @@ use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
use smoltcp::time::Instant;
use smoltcp::socket::SocketSet;
use smoltcp::socket::{TcpSocket, TcpSocketBuffer};
use libboard_zynq::{print, println, self as zynq};
mod boot;
mod regs;
mod cortex_a9;
mod abort;
mod panic;
mod zynq;
mod stdio;
mod ram;
use cortex_a9::mutex::Mutex;
use libcortex_a9::mutex::Mutex;
const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
@ -36,8 +30,10 @@ static mut STACK_CORE1: [u32; 512] = [0; 512];
pub fn main() {
// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
println!("\nzc706 main");
use regs::RegisterR;
println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
{
use libregister::RegisterR;
println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
}
let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
@ -110,7 +106,7 @@ pub fn main() {
core1.stop();
cortex_a9::asm::dsb();
libcortex_a9::asm::dsb();
print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
for w in core1.stack {
print!(" {:08X}", w);

0
src/main.rs.orig → libboard_zc706/src/main.rs.orig
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4
src/panic.rs → libboard_zc706/src/panic.rs
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@ -1,4 +1,4 @@
use crate::{print, println, zynq};
use libboard_zynq::{slcr, print, println};
#[panic_handler]
fn panic(info: &core::panic::PanicInfo) -> ! {
@ -14,6 +14,6 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
println!("");
}
zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
loop {}
}

4
src/ram.rs → libboard_zc706/src/ram.rs
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@ -2,8 +2,8 @@ use core::alloc::GlobalAlloc;
use core::ptr::NonNull;
use alloc::alloc::Layout;
use linked_list_allocator::Heap;
use crate::cortex_a9::mutex::Mutex;
use crate::zynq::ddr::DdrRam;
use libcortex_a9::mutex::Mutex;
use libboard_zynq::ddr::DdrRam;
#[global_allocator]
static ALLOCATOR: CortexA9Alloc = CortexA9Alloc(Mutex::new(Heap::empty()));

25
libboard_zynq/Cargo.toml Normal file
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@ -0,0 +1,25 @@
[package]
name = "libboard_zynq"
version = "0.0.0"
authors = ["Astro <astro@spaceboyz.net>"]
edition = "2018"
[features]
target_zc706 = []
target_cora_z7_10 = []
default = ["target_zc706"]
[dependencies]
r0 = "0.2"
vcell = "0.1"
volatile-register = "0.2"
bit_field = "0.10"
linked_list_allocator = { version = "0.6", default-features = false }
libregister = { path = "../libregister" }
libcortex_a9 = { path = "../libcortex_a9" }
[dependencies.smoltcp]
git = "https://github.com/m-labs/smoltcp.git"
rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
features = ["ethernet", "proto-ipv4", "socket-tcp"]
default-features = false

0
src/zynq/axi_gp.rs → libboard_zynq/src/axi_gp.rs
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2
src/zynq/axi_hp.rs → libboard_zynq/src/axi_hp.rs
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@ -2,7 +2,7 @@
use volatile_register::RW;
use crate::{register, register_bit, register_bits};
use libregister::{register, register_bit, register_bits};
pub unsafe fn axi_hp0() -> &'static RegisterBlock {
&*(0xF8008000 as *const _)

2
src/zynq/clocks.rs → libboard_zynq/src/clocks.rs
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@ -1,4 +1,4 @@
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use libregister::{RegisterR, RegisterW, RegisterRW};
use super::slcr;
#[cfg(feature = "target_zc706")]

2
src/zynq/ddr/mod.rs → libboard_zynq/src/ddr/mod.rs
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@ -1,4 +1,4 @@
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use libregister::{RegisterR, RegisterW, RegisterRW};
use crate::{print, println};
use super::slcr;
use super::clocks::CpuClocks;

3
src/zynq/ddr/regs.rs → libboard_zynq/src/ddr/regs.rs
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@ -1,7 +1,8 @@
use volatile_register::{RO, RW};
use crate::{register, register_bit, register_bits_typed};
use libregister::{register, register_bit, register_bits_typed};
#[allow(unused)]
#[repr(u8)]
pub enum DataBusWidth {
Width32bit = 0b00,

2
src/zynq/eth/mod.rs → libboard_zynq/src/eth/mod.rs
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@ -1,4 +1,4 @@
use crate::regs::*;
use libregister::*;
use crate::println;
use super::slcr;
use super::clocks::CpuClocks;

0
src/zynq/eth/phy/control.rs → libboard_zynq/src/eth/phy/control.rs
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0
src/zynq/eth/phy/extended_status.rs → libboard_zynq/src/eth/phy/extended_status.rs
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0
src/zynq/eth/phy/id.rs → libboard_zynq/src/eth/phy/id.rs
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0
src/zynq/eth/phy/mod.rs → libboard_zynq/src/eth/phy/mod.rs
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0
src/zynq/eth/phy/status.rs → libboard_zynq/src/eth/phy/status.rs
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2
src/zynq/eth/regs.rs → libboard_zynq/src/eth/regs.rs
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@ -1,6 +1,6 @@
use volatile_register::{RO, WO, RW};
use crate::{register, register_bit, register_bits, register_bits_typed};
use libregister::{register, register_bit, register_bits, register_bits_typed};
#[repr(C)]
pub struct RegisterBlock {

3
src/zynq/eth/rx.rs → libboard_zynq/src/eth/rx.rs
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@ -1,6 +1,5 @@
use core::ops::Deref;
use vcell::VolatileCell;
use crate::{register, register_bit, register_bits, regs::*};
use libregister::*;
use super::MTU;
#[derive(Debug)]

3
src/zynq/eth/tx.rs → libboard_zynq/src/eth/tx.rs
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@ -1,6 +1,5 @@
use core::ops::{Deref, DerefMut};
use vcell::VolatileCell;
use crate::{register, register_bit, register_bits, regs::*};
use libregister::*;
use super::{MTU, regs};
/// Descriptor entry

0
src/zynq/flash/bytes.rs → libboard_zynq/src/flash/bytes.rs
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2
src/zynq/flash/mod.rs → libboard_zynq/src/flash/mod.rs
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@ -2,7 +2,7 @@
use crate::{print, println};
use core::marker::PhantomData;
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use libregister::{RegisterR, RegisterW, RegisterRW};
use super::slcr;
use super::clocks::CpuClocks;

2
src/zynq/flash/regs.rs → libboard_zynq/src/flash/regs.rs
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@ -1,6 +1,6 @@
use volatile_register::{RO, WO, RW};
use crate::{register, register_bit, register_bits};
use libregister::{register, register_bit, register_bits};
#[repr(C)]
pub struct RegisterBlock {

1
src/zynq/flash/spi_flash_register.rs → libboard_zynq/src/flash/spi_flash_register.rs
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@ -26,6 +26,7 @@ macro_rules! u8_register {
}
impl $name {
#[allow(unused)]
pub fn is_zeroed(&self) -> bool {
self.inner == 0
}

2
src/zynq/flash/transfer.rs → libboard_zynq/src/flash/transfer.rs
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@ -1,4 +1,4 @@
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use libregister::{RegisterR, RegisterW, RegisterRW};
use super::regs;
use super::{SpiWord, Flash, Manual};

3
src/zynq/mod.rs → libboard_zynq/src/lib.rs
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@ -1,6 +1,9 @@
#![no_std]
pub mod slcr;
pub mod clocks;
pub mod uart;
pub mod stdio;
pub mod eth;
pub mod axi_hp;
pub mod axi_gp;

6
src/zynq/mpcore.rs → libboard_zynq/src/mpcore.rs
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@ -1,8 +1,10 @@
///! Register definitions for Application Processing Unit (mpcore)
use volatile_register::{RO, RW};
use crate::{register, register_at, register_bit, register_bits,
regs::RegisterW, regs::RegisterRW};
use libregister::{
register, register_at, register_bit, register_bits,
RegisterW, RegisterRW,
};
#[repr(C)]
pub struct RegisterBlock {

8
src/zynq/slcr.rs → libboard_zynq/src/slcr.rs
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@ -1,9 +1,11 @@
///! Register definitions for System Level Control
use volatile_register::{RO, RW};
use crate::{register, register_at,
register_bit, register_bits, register_bits_typed,
regs::RegisterW, regs::RegisterRW};
use libregister::{
register, register_at,
register_bit, register_bits, register_bits_typed,
RegisterW, RegisterRW,
};
#[repr(u8)]
pub enum PllSource {

8
src/stdio.rs → libboard_zynq/src/stdio.rs
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@ -1,6 +1,6 @@
use core::ops::{Deref, DerefMut};
use crate::cortex_a9::mutex::{Mutex, MutexGuard};
use crate::zynq::uart::Uart;
use libcortex_a9::mutex::{Mutex, MutexGuard};
use crate::uart::Uart;
const UART_RATE: u32 = 115_200;
static mut UART: Mutex<LazyUart> = Mutex::new(LazyUart::Uninitialized);
@ -47,7 +47,7 @@ impl DerefMut for LazyUart {
macro_rules! print {
($($arg:tt)*) => ({
use core::fmt::Write;
let mut uart = crate::stdio::get_uart();
let mut uart = $crate::stdio::get_uart();
let _ = write!(uart, $($arg)*);
})
}
@ -56,7 +56,7 @@ macro_rules! print {
macro_rules! println {
($($arg:tt)*) => ({
use core::fmt::Write;
let mut uart = crate::stdio::get_uart();
let mut uart = $crate::stdio::get_uart();
let _ = write!(uart, $($arg)*);
let _ = write!(uart, "\r\n");
while !uart.tx_fifo_empty() {}

2
src/zynq/uart/baud_rate_gen.rs → libboard_zynq/src/uart/baud_rate_gen.rs
View File

@ -1,4 +1,4 @@
use crate::regs::*;
use libregister::*;
use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv};
const BDIV_MIN: u32 = 4;

2
src/zynq/uart/mod.rs → libboard_zynq/src/uart/mod.rs
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@ -1,6 +1,6 @@
use core::fmt;
use crate::regs::*;
use libregister::*;
use super::slcr;
use super::clocks::CpuClocks;

8
src/zynq/uart/regs.rs → libboard_zynq/src/uart/regs.rs
View File

@ -1,7 +1,11 @@
use volatile_register::{RO, WO, RW};
use crate::{register, register_bit, register_bits, register_bits_typed, register_at};
use libregister::{
register, register_at,
register_bit, register_bits, register_bits_typed,
};
#[allow(unused)]
#[repr(u8)]
pub enum ChannelMode {
Normal = 0b00,
@ -10,6 +14,7 @@ pub enum ChannelMode {
RemoteLoopback = 0b11,
}
#[allow(unused)]
#[repr(u8)]
pub enum ParityMode {
EvenParity = 0b000,
@ -19,6 +24,7 @@ pub enum ParityMode {
None = 0b100,
}
#[allow(unused)]
#[repr(u8)]
pub enum StopBits {
One = 0b00,

23
libcortex_a9/Cargo.toml Normal file
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@ -0,0 +1,23 @@
[package]
name = "libcortex_a9"
version = "0.0.0"
authors = ["Astro <astro@spaceboyz.net>"]
edition = "2018"
[features]
target_zc706 = []
target_cora_z7_10 = []
default = ["target_zc706"]
[dependencies]
r0 = "0.2"
vcell = "0.1"
volatile-register = "0.2"
bit_field = "0.10"
libregister = { path = "../libregister" }
[dependencies.smoltcp]
git = "https://github.com/m-labs/smoltcp.git"
rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
features = ["ethernet", "proto-ipv4", "socket-tcp"]
default-features = false

0
src/cortex_a9/asm.rs → libcortex_a9/src/asm.rs
View File

0
src/cortex_a9/cache.rs → libcortex_a9/src/cache.rs
View File

0
src/cortex_a9/exceptions.s → libcortex_a9/src/exceptions.s
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4
src/cortex_a9/mod.rs → libcortex_a9/src/lib.rs
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@ -1,3 +1,7 @@
#![no_std]
#![feature(asm, global_asm)]
#![feature(never_type)]
pub mod asm;
pub mod regs;
pub mod cache;

2
src/cortex_a9/mmu.rs → libcortex_a9/src/mmu.rs
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@ -1,6 +1,6 @@
use bit_field::BitField;
use super::{regs::*, asm};
use crate::regs::RegisterW;
use libregister::RegisterW;
#[derive(Copy, Clone)]
#[repr(u8)]

0
src/cortex_a9/mutex.rs → libcortex_a9/src/mutex.rs
View File

6
src/cortex_a9/regs.rs → libcortex_a9/src/regs.rs
View File

@ -1,5 +1,7 @@
use crate::{register_bit, register_bits};
use crate::regs::{RegisterR, RegisterW, RegisterRW};
use libregister::{
register_bit, register_bits,
RegisterR, RegisterW, RegisterRW,
};
macro_rules! def_reg_r {
($name:tt, $type: ty, $asm_instr:tt) => {

10
libregister/Cargo.toml Normal file
View File

@ -0,0 +1,10 @@
[package]
name = "libregister"
version = "0.0.0"
authors = ["Astro <astro@spaceboyz.net>"]
edition = "2018"
[dependencies]
vcell = "0.1"
volatile-register = "0.2"
bit_field = "0.10"

41
src/regs.rs → libregister/src/lib.rs
View File

@ -1,10 +1,11 @@
//! Type-safe interface to peripheral registers akin to the code that
//! svd2rust generates.
#![allow(unused)]
use vcell::VolatileCell;
use volatile_register::{RO, WO, RW};
use bit_field::BitField;
#![no_std]
pub use vcell::VolatileCell;
pub use volatile_register::{RO, WO, RW};
pub use bit_field::BitField;
/// A readable register
pub trait RegisterR {
@ -51,7 +52,7 @@ macro_rules! register_common {
#[macro_export]
macro_rules! register_r {
($mod_name: ident, $struct_name: ident) => (
impl crate::regs::RegisterR for $struct_name {
impl libregister::RegisterR for $struct_name {
type R = $mod_name::Read;
fn read(&self) -> Self::R {
@ -65,7 +66,7 @@ macro_rules! register_r {
#[macro_export]
macro_rules! register_w {
($mod_name: ident, $struct_name: ident) => (
impl crate::regs::RegisterW for $struct_name {
impl libregister::RegisterW for $struct_name {
type W = $mod_name::Write;
fn zeroed() -> $mod_name::Write {
@ -84,7 +85,7 @@ macro_rules! register_w {
#[macro_export]
macro_rules! register_rw {
($mod_name: ident, $struct_name: ident) => (
impl crate::regs::RegisterRW for $struct_name {
impl libregister::RegisterRW for $struct_name {
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
unsafe {
self.inner.modify(|inner| {
@ -101,7 +102,7 @@ macro_rules! register_rw {
#[macro_export]
macro_rules! register_vcell {
($mod_name: ident, $struct_name: ident) => (
impl crate::regs::RegisterR for $struct_name {
impl libregister::RegisterR for $struct_name {
type R = $mod_name::Read;
fn read(&self) -> Self::R {
@ -109,7 +110,7 @@ macro_rules! register_vcell {
$mod_name::Read { inner }
}
}
impl crate::regs::RegisterW for $struct_name {
impl libregister::RegisterW for $struct_name {
type W = $mod_name::Write;
fn zeroed() -> $mod_name::Write {
@ -120,7 +121,7 @@ macro_rules! register_vcell {
self.inner.set(w.inner);
}
}
impl crate::regs::RegisterRW for $struct_name {
impl libregister::RegisterRW for $struct_name {
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
let r = self.read();
let w = $mod_name::Write { inner: r.inner };
@ -136,28 +137,28 @@ macro_rules! register_vcell {
macro_rules! register {
// Define read-only register
($mod_name: ident, $struct_name: ident, RO, $inner: ty) => (
crate::register_common!($mod_name, $struct_name, volatile_register::RO<$inner>, $inner);
crate::register_r!($mod_name, $struct_name);
libregister::register_common!($mod_name, $struct_name, libregister::RO<$inner>, $inner);
libregister::register_r!($mod_name, $struct_name);
);
// Define write-only register
($mod_name: ident, $struct_name: ident, WO, $inner: ty) => (
crate::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner);
crate::register_w!($mod_name, $struct_name);
libregister::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner);
libregister::register_w!($mod_name, $struct_name);
);
// Define read-write register
($mod_name: ident, $struct_name: ident, RW, $inner: ty) => (
crate::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
crate::register_r!($mod_name, $struct_name);
crate::register_w!($mod_name, $struct_name);
crate::register_rw!($mod_name, $struct_name);
libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
libregister::register_r!($mod_name, $struct_name);
libregister::register_w!($mod_name, $struct_name);
libregister::register_rw!($mod_name, $struct_name);
);
// Define read-write register
($mod_name: ident, $struct_name: ident, VolatileCell, $inner: ty) => (
crate::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
crate::register_vcell!($mod_name, $struct_name);
libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
libregister::register_vcell!($mod_name, $struct_name);
);
}