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zynq-rs
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fix UART_REF_CLK 

started to become garbled.
This commit is contained in:
Astro 2019-08-07 00:27:01 +02:00
parent 66c3470afd
commit b7690c9702
1 changed files with 2 additions and 2 deletions
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4
src/uart/mod.rs
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@ -10,9 +10,9 @@ mod baud_rate_gen;
/// Determined through experimentation. Actually supposed to be /// Determined through experimentation. Actually supposed to be
/// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz. /// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz.
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
const UART_REF_CLK: u32 = 45_000_000; const UART_REF_CLK: u32 = 50_000_000;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_cora_z7_10")]
const UART_REF_CLK: u32 = 66_000_000; const UART_REF_CLK: u32 = 72_000_000;
pub struct Uart { pub struct Uart {
regs: &'static mut regs::RegisterBlock, regs: &'static mut regs::RegisterBlock,