ddr: remove superfluous `_reg` from register names
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6195ad40c3
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b2c707d543
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@ -210,7 +210,7 @@ impl DdrRam {
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}
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pub fn status(&self) -> regs::ControllerStatus {
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self.regs.mode_sts_reg.read().operating_mode()
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self.regs.mode_sts.read().operating_mode()
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}
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pub fn ptr<T>(&mut self) -> *mut T {
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@ -29,59 +29,59 @@ pub enum ControllerStatus {
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pub struct RegisterBlock {
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pub ddrc_ctrl: DdrcCtrl,
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pub two_rank_cfg: RW<u32>,
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pub hpr_reg: RW<u32>,
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pub lpr_reg: RW<u32>,
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pub wr_reg: RW<u32>,
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pub dram_param_reg0: RW<u32>,
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pub dram_param_reg1: RW<u32>,
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pub dram_param_reg2: RW<u32>,
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pub dram_param_reg3: RW<u32>,
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pub dram_param_reg4: RW<u32>,
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pub hpr: RW<u32>,
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pub lpr: RW<u32>,
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pub wr: RW<u32>,
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pub dram_param0: RW<u32>,
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pub dram_param1: RW<u32>,
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pub dram_param2: RW<u32>,
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pub dram_param3: RW<u32>,
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pub dram_param4: RW<u32>,
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pub dram_init_param: RW<u32>,
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pub dram_emr_reg: RW<u32>,
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pub dram_emr_mr_reg: RW<u32>,
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pub dram_emr: RW<u32>,
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pub dram_emr_mr: RW<u32>,
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pub dram_burst8_rdwr: RW<u32>,
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pub dram_disable_dq: RW<u32>,
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pub dram_addr_map_bank: RW<u32>,
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pub dram_addr_map_col: RW<u32>,
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pub dram_addr_map_row: RW<u32>,
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pub dram_odt_reg: RW<u32>,
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pub phy_dbg_reg: RW<u32>,
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pub dram_odt: RW<u32>,
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pub phy_dbg: RW<u32>,
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pub phy_cmd_timeout_rddata_cpt: RW<u32>,
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pub mode_sts_reg: ModeStsReg,
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pub mode_sts: ModeStsReg,
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pub dll_calib: RW<u32>,
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pub odt_delay_hold: RW<u32>,
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pub ctrl_reg1: RW<u32>,
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pub ctrl_reg2: RW<u32>,
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pub ctrl_reg3: RW<u32>,
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pub ctrl_reg4: RW<u32>,
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pub ctrl1: RW<u32>,
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pub ctrl2: RW<u32>,
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pub ctrl3: RW<u32>,
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pub ctrl4: RW<u32>,
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_unused0: [RO<u32>; 2],
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pub ctrl_reg5: RW<u32>,
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pub ctrl_reg6: RW<u32>,
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pub ctrl5: RW<u32>,
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pub ctrl6: RW<u32>,
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_unused1: [RO<u32>; 8],
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pub che_refresh_timer01: RW<u32>,
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pub che_t_zq: RW<u32>,
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pub che_t_zq_short_interval_reg: RW<u32>,
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pub deep_pwrdwn_reg: RW<u32>,
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pub che_t_zq_short_interval: RW<u32>,
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pub deep_pwrdwn: RW<u32>,
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pub reg_2c: RW<u32>,
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pub reg_2d: RW<u32>,
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pub dfi_timing: RW<u32>,
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_unused2: [RO<u32>; 2],
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pub che_ecc_control_reg_offset: RW<u32>,
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pub che_corr_ecc_log_reg_offset: RW<u32>,
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pub che_corr_ecc_addr_reg_offset: RW<u32>,
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pub che_corr_ecc_data_31_0_reg_offset: RW<u32>,
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pub che_corr_ecc_data_63_32_reg_offset: RW<u32>,
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pub che_corr_ecc_data_71_64_reg_offset: RW<u32>,
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pub che_uncorr_ecc_log_reg_offset: RW<u32>,
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pub che_uncorr_ecc_addr_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_31_0_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_63_32_reg_offset: RW<u32>,
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pub che_uncorr_ecc_data_71_64_reg_offset: RW<u32>,
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pub che_ecc_stats_reg_offset: RW<u32>,
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pub che_ecc_control_offset: RW<u32>,
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pub che_corr_ecc_log_offset: RW<u32>,
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pub che_corr_ecc_addr_offset: RW<u32>,
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pub che_corr_ecc_data_31_0_offset: RW<u32>,
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pub che_corr_ecc_data_63_32_offset: RW<u32>,
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pub che_corr_ecc_data_71_64_offset: RW<u32>,
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pub che_uncorr_ecc_log_offset: RW<u32>,
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pub che_uncorr_ecc_addr_offset: RW<u32>,
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pub che_uncorr_ecc_data_31_0_offset: RW<u32>,
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pub che_uncorr_ecc_data_63_32_offset: RW<u32>,
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pub che_uncorr_ecc_data_71_64_offset: RW<u32>,
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pub che_ecc_stats_offset: RW<u32>,
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pub ecc_scrub: RW<u32>,
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pub che_ecc_corr_bit_mask_31_0_reg_offset: RW<u32>,
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pub che_ecc_corr_bit_mask_63_32_reg_offset: RW<u32>,
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pub che_ecc_corr_bit_mask_31_0_offset: RW<u32>,
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pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
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_unused3: [RO<u32>; 5],
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pub phy_rcvr_enable: RW<u32>,
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pub phy_config0: RW<u32>,
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@ -134,7 +134,7 @@ pub struct RegisterBlock {
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_unused13: RO<u32>,
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pub dll_lock_sts: RW<u32>,
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pub phy_ctrl_sts: RW<u32>,
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pub phy_ctrl_sts_reg2: RW<u32>,
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pub phy_ctrl_sts2: RW<u32>,
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_unused14: [RO<u32>; 5],
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pub axi_id: RW<u32>,
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pub page_mask: RW<u32>,
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@ -151,7 +151,7 @@ pub struct RegisterBlock {
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pub excl_access_cfg1: RW<u32>,
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pub excl_access_cfg2: RW<u32>,
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pub excl_access_cfg3: RW<u32>,
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pub mode_reg_read: RW<u32>,
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pub mode_read: RW<u32>,
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pub lpddr_ctrl0: RW<u32>,
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pub lpddr_ctrl1: RW<u32>,
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pub lpddr_ctrl2: RW<u32>,
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