M-Labs/zynq-rs
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reduce ethernet verbosity

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This commit is contained in:
Sebastien Bourdeauducq 2020-08-04 22:15:01 +08:00
parent 25c6d5eeaa
commit a36a82d86d
1 changed files with 5 additions and 5 deletions
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10
libboard_zynq/src/eth/mod.rs
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@ -2,7 +2,7 @@ use core::{
marker::PhantomData,
ops::{Deref, DerefMut},
};
use log::{error, info, warn};
use log::{debug, info, warn, error};
use libregister::*;
use super::slcr;
use super::clocks::Clocks;
@ -132,10 +132,10 @@ fn calculate_tx_divisors(tx_clock: u32) -> (u8, u8) {
}
}
let result = best.unwrap();
info!("Eth TX clock for {}: {} / {} / {} = {}",
tx_clock, io_pll,
result.0, result.1,
io_pll / result.0 as u32 / result.1 as u32
debug!("Eth TX clock for {}: {} / {} / {} = {}",
tx_clock, io_pll,
result.0, result.1,
io_pll / result.0 as u32 / result.1 as u32
);
result
}