M-Labs/zynq-rs
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i2c: fix SCL/SDA race conditions & handle slave holding SCL after ack

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This commit is contained in:
Harry Ho 2021-06-23 17:07:58 +08:00
parent 040d41fd76
commit 91445620ee
1 changed files with 7 additions and 1 deletions
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8
libboard_zynq/src/i2c/mod.rs
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@ -150,16 +150,18 @@ impl I2c {
self.sda_oe(true); self.sda_oe(true);
self.half_period(); self.half_period();
self.scl_oe(true); self.scl_oe(true);
while self.scl_i() {} // ensure SCL is low before start() returns
// postcondition: SCL and SDA low // postcondition: SCL and SDA low
Ok(()) Ok(())
} }
pub fn restart(&mut self) -> Result<(), &'static str> { pub fn restart(&mut self) -> Result<(), &'static str> {
// precondition SCL and SDA low // precondition: any
self.sda_oe(false); self.sda_oe(false);
self.half_period(); self.half_period();
self.scl_oe(false); self.scl_oe(false);
self.half_period(); self.half_period();
// enter the precondition for start(): SCL and SDA high
self.start()?; self.start()?;
// postcondition: SCL and SDA low // postcondition: SCL and SDA low
Ok(()) Ok(())
@ -188,6 +190,7 @@ impl I2c {
self.scl_oe(false); self.scl_oe(false);
self.half_period(); self.half_period();
self.scl_oe(true); self.scl_oe(true);
while self.scl_i() {} // ensure SCL is low before start() returns
} }
self.sda_oe(false); self.sda_oe(false);
self.half_period(); self.half_period();
@ -196,6 +199,7 @@ impl I2c {
// Read ack/nack // Read ack/nack
let ack = !self.sda_i(); let ack = !self.sda_i();
self.scl_oe(true); self.scl_oe(true);
while self.scl_i() {} // ensure SCL is low before start() returns
self.sda_oe(true); self.sda_oe(true);
// postcondition: SCL and SDA low // postcondition: SCL and SDA low
@ -215,6 +219,7 @@ impl I2c {
self.half_period(); self.half_period();
if self.sda_i() { data |= 1 << bit } if self.sda_i() { data |= 1 << bit }
self.scl_oe(true); self.scl_oe(true);
while self.scl_i() {} // ensure SCL is low before start() returns
} }
// Send ack/nack // Send ack/nack
self.sda_oe(ack); self.sda_oe(ack);
@ -222,6 +227,7 @@ impl I2c {
self.scl_oe(false); self.scl_oe(false);
self.half_period(); self.half_period();
self.scl_oe(true); self.scl_oe(true);
while self.scl_i() {} // ensure SCL is low before start() returns
self.sda_oe(true); self.sda_oe(true);
// postcondition: SCL and SDA low // postcondition: SCL and SDA low