Add core0 interrupt return test
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40b3d2e057
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@ -56,10 +56,18 @@ extern "C" {
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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let id = gic.get_interrupt_id();
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match MPIDR.read().cpu_id(){
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0 => {
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if id.0 == 0 {
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println!("Interrupting core0...");
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gic.end_interrupt(id);
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return;
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}
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},
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1 => {
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if id.0 == 0 {
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if id.0 == 0 {
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gic.end_interrupt(id);
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gic.end_interrupt(id);
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asm::exit_irq();
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asm::exit_irq();
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@ -69,6 +77,8 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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notify_spin_lock();
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notify_spin_lock();
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main_core1();
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main_core1();
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}
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}
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},
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_ => {}
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}
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}
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stdio::drop_uart();
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stdio::drop_uart();
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println!("IRQ");
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println!("IRQ");
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@ -134,6 +144,10 @@ pub fn main_core0() {
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ddr.memtest();
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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ram::init_alloc_ddr(&mut ddr);
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info!("Send software interrupt to core0");
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core0.into());
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info!("Core0 returned from interrupt");
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boot::Core1::start(false);
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boot::Core1::start(false);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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